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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN8804 датащи(PDF) 45 Page - Microchip Technology |
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LAN8804 датащи(HTML) 45 Page - Microchip Technology |
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45 / 91 page  LAN8804 © 2024 Microchip Technology Inc. and its subsidiaries DS00003591G-page 45 5.13 QSGMII The device provides a QSGMII interface that adheres to the QSGMII Specification Rev. 1.3 [4] (EDCS-540123). QSGMII is a serial chip-chip connection that connects the LAN8804 PHY ports with four MACs in the Switch or SoC. Figure 5-7 illustrates QSGMII operation, with the switch/SoC on the left and the LAN8804 on the right. Each device PHY connects to an SGMII “PCS1G” block (each is shown in Figure 5-7 as a separate TX PCS1G and RX PCS1G). The four SGMII TX PCS1G outputs are multiplexed together by the TX QSGMII Extender, which then swaps the Port 0 K28.5 symbol to K28.1 for Port 0 in the TX QSGMII Extender, before multiplexing the four ports together. Each PCS1G instance includes a Jitter Test Pattern (JTP) Generator and Checker. The JTP Generator supports the following test patterns: • High Frequency Test Pattern – repeated transmission of D21.5 code group • Low Frequency Test Pattern – repeated transmission of K28.7 code group • Mixed Frequency Test Pattern – repeated transmission of K28.5 code group • Long Continuous Random Test Pattern – 1524 byte frames • Short Continuous Random Test Pattern – 360 byte frames The JTP Checker provides Checker Lock and Error Detected indications, as well as an error count. FIGURE 5-7: QSGMII SYSTEM DIAGRAM QSGMII TX RX PCS RX PMA RX AFE TX PCS1G 8 8 10 20 1 RX PCS RX PMA RX AFE TX PCS1G 8 8 10 RX PCS RX PMA RX AFE TX PCS1G 8 8 10 RX PCS RX PMA RX AFE TX PCS1G 8 8 10 RX0 Timing Domain RX1 Timing Domain RX2 Timing Domain RX3 Timing Domain QSGMII TX Timing Domain QSGMII RX TX PCS TX PMA TX AFE RX PCS1G 8 8 10 20 1 TX PCS TX PMA TX AFE RX PCS1G 8 8 10 TX PCS TX PMA TX AFE RX PCS1G 8 8 10 TX PCS TX PMA TX AFE RX PCS1G 8 8 10 TX0 Timing Domain TX1 Timing Domain TX2 Timing Domain TX3 Timing Domain QSGMII RX Timing Domain 5 Gbps 250 MHz 125 MHz 125 MHz TX PCS1G Rate Adaptation TX PCS1G Rate Adaptation TX PCS1G Rate Adaptation TX PCS1G Rate Adaptation RX PCS1G Rate Adaptation RX PCS1G Rate Adaptation RX PCS1G Rate Adaptation RX PCS1G Rate Adaptation PHY RX Timing Domains PHY TX Timing Domains PHY RX PHY TX RX0 RX1 RX2 RX3 TX0 TX1 TX2 TX3 |
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