LAN8804 datasheet(18/91 Pages) MICROCHIP

18 / 91 page

LAN8804

DS00003591G-page 18

Port 2 LED 2

PORT2LED2

VO12/

VOD12/

VOS12

Programmable Port 2 LED 2 output.

The polarity of this pin depends on the

PORT2_LED2_POL

configuration strap which is shared with this pin.

Port 3 LED 1

PORT3LED1

VO12/

VOD12/

VOS12

Programmable Port 3 LED 1 output.

The polarity of this pin depends on the

PORT3_LED1_POL

configuration strap which is shared with this pin.

Port 3 LED 2

PORT3LED2

VO12/

VOD12/

VOS12

Programmable Port 3 LED 2 output.

The polarity of this pin depends on the

PORT3_LED2_POL

configuration strap which is shared with this pin.

Coma Mode

Control

COMA_MODE

VIS

(PU)

Drive high to activate Coma mode. After all ports are config-

ured, drive low to enable normal operation. Hold low to disable

this feature.

Reference Clock

Select

REF_CLK_SEL[1:0]

VIS

These pins control reference clock selection of the System

PLL and QSGMII SerDes MPLL.

REF_CLK_SEL[1:0]

00: SYSPLL Reference 25 MHz from XI/XO

QSGMII Reference 25 MHz from

XI/XO

01: RESERVED

10: SYSPLL Reference 25 MHz from CK125_REF_INP/M

QSGMII Reference 125 MHz from

CK125_REF_INP/M

11: RESERVED

Note:

These are live pins, not configuration straps, and

must be permanently tied high/low.

Note:

XI/XO can be a 25 MHz crystal or a 25 MHz exter-

nal clock.

CK125_REF_INP/M is a 125 MHz exter-

nal clock.

System Clock

Output Enable

CK25OUT_EN

VIS

CK25OUT enable/disable:

0: Disabled

1: Enabled

Note:

This is a live pin, not a configuration strap.

QSGMII SerDes

Voltage Regulator

Bypass

VREG_BYPASS

VIS

QSGMII SerDes voltage regulator bypass:

0: SerDes powered from internal 3.3V to 2.5V regulator

(regulator in use)

1: SerDes powered directly from 2.5V (regulator bypassed)

Note:

This pin must be permanently tied high/low.

LDO Controller

Output

LDO_O

On-chip +1.1V LDO controller output. This pin drives the input

gate of a P-channel MOSFET to generate +1.1V for the

device’s core voltages.

Note:

If the system provides 1.1V, this pin is not used and

can be left unconnected.

SerDes Bias

Resistor

RES_REF

This pin must be connected to ground through a 200 Ω 1%

100ppm/C resistor.

PHY Bias Resistor

ISET

This pin must be connected to ground through a 6.04 kΩ 1%

resistor.

TABLE 3-5:

MISCELLANEOUS PINS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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