SAA7780 datasheet(35/70 Pages) PHILIPS

35 / 70 page

ThunderBird Q3D PCI Audio

SAA7780

Accelerator

Philips Semiconductors

Product Specification

1999 Sep 30

Note: An RC indicates that this bit can be reset to 0 by writing a 1. Writing a zero leaves this bit unchanged.

POR Value

BK2BK

UDF

MHz66

POR Value

Bit

Name

R/W

Function

R_PERR

Received Parity Error: When set to 1, this bit indicates that the SAA7780,

function 0 has detected a PCI bus parity error at least once since this bit was

last reset.

S_SERR

Signalled System Error: When set to 1, this bit indicates that the SAA7780,

function 0 has reported a system error on the SERR# signal at least once

since this bit was last reset.

SM_ABORT

Signalled Master Abort: When set to 1, this bit indicates that the SAA7780,

function 0 (acting as a master) had to initiate a master abort at least once

since this bit was last reset.

RT_ABORT

Received Target Abort: When set to 1, this bit indicates that the SAA7780,

function 0 (acting as a master) has received a target abort at least once since

this bit was last reset.

ST_ABORT

Signalled Target Abort: When set to 1, this bit indicates that the SAA7780,

function 0 has signalled a target abort at least once since this bit was last

reset.

10:9

DEVSEL_TM

DEVSEL Timing: This field indicates the timing of the DEVSEL output (when

a PCI master is accessing a SAA7780, function 0 resource). It always returns

01 (Bin).

00 = Fast

01 = Medium (Default Timing)

10 = Slow

S_PERR

Signalled Parity Error: When set to 1, this bit indicates that the SAA7780,

function 0 was a bus master for a cycle in which PERR# was activated. This

bit cannot be set if the PERR_RESP bit in the command register is not

enabled.

F_BK2BK

Always returns 1 to indicate support of fast back to back cycles when the

SAA7780, function 0 is the target.

UDF

User Definable Features. Always returns 0.

MHz66

66 MHz Capable. Always returns 0.

4:0

Reserved. These bits always return zero.

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