SAA7780 datasheet(44/70 Pages) PHILIPS

44 / 70 page

ThunderBird Q3D PCI Audio

SAA7780

Accelerator

Philips Semiconductors

Product Specification

1999 Sep 30

MAX_LAT Register - MAXLAT (RO)

SAA7780 CFG Space 0 DMA Base Registers

This section will describe the PCI configuration registers that provide functions such as base address remapping and

the like. These registers reside within the PCI interface.

DMA Channel A Base Address Register - DMAABASE (RW)

Bit

Name

R/W

Function

7:0

MINGNT

Minimum grant specifies how long of a burst period the device needs

assuming a clock speed of 33MHz. Since the SAA7780, function 0, will burst

a maximum of 64 double words, therefore requiring about 75 33MHz clocks

or 2.25 microseconds. The time units specified are in 0.25 microsecond

increments.

PCI CFG 0

Offset 3Fh

MAXLAT[7:0]

POR Value

Bit

Name

R/W

Function

7:0

MAXLAT

Maximum latency specifies how often a device needs to gain access to the

PCI bus. The SAA7780, function 0, should only request the bus a a

maximum of every 10 microseconds. The MAXLAT value is computed using

the same parameters as the MINGNT.

PCI CFG 0

D15

D14

D13

D12

D11

D10

Offset 40h

DMAABASE[15:8]

POR Value

DMAA

BASE[7]

DMAABASE[5:4]

XFRSIZ[1:0]

DDMAA

POR Value

Bit

Name

R/W

Function

15:7

DMAABASE

DMA channel A programmable base address, bits 15:7.

Reserved. This bit must always be zero.

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