SAA7780 datasheet(18/70 Pages) PHILIPS

18 / 70 page

ThunderBird Q3D PCI Audio

SAA7780

Accelerator

Philips Semiconductors

Product Specification

1999 Sep 30

GNT#

I-T

PCI Bus Grant

An asserted GNT# pin indicates that the PCI master arbiter has

granted bus ownership to the SAA7780 chip.

IRQSER

IO-OD

PCI Bus Serial Interrupts

This pin is used to output the serial interrupt stream for legacy

interrupts. It is used only if the SAA7780 is used in a Common

Architecture system. Otherwise it is tri-stated.

INTA#

IO-OD

PCI Bus Interrupt A

The interrupt output is a PCI compatible active low level sensitive

interrupt. It is only used if the SAA7780 is used in a non Common

Architecture system. Otherwise it is tri-stated. It is driven low when

any of the internal interrupts are asserted.

PERR#

IO-STS

PCI Bus Parity Error

This signal indicates a data parity error for any cycle type other than

a Special Cycle command. PERR# is made active two clocks after

the completion of the data phase which caused the parity error. This

error signal may result in the generation of a non-maskable interrupt

(NMI) or other high priority interrupt sent to the CPU.

SERR#

IO-OD

PCI Bus System Error

This signal indicates an address parity error, data parity errors on

Special Cycle commands or any other catastrophic system error.

SERR# is an open-drain bidirectional pin which is driven low for a

single PCLK cycle by the agent reporting the error. This error may

result in the generation of a non-maskable interrupt (NMI) or other

high priority interrupt sent to the CPU.

IDSEL

I-T

Initialization Device Select

IDSEL is used as a chip select during configuration register read

and write operations. One system board address line from

AD[31:11] is used as IDSEL to select the SAA7780 configuration

space in the SAA7780 chip when used on the PCI bus.

CLKRUN#

100

O-OD

PCI Bus Clock Run Request

The SAA7780 uses CLKRUN# according to the Mobile PCI protocol

to start the PCI clock or keep the clock running whenever an internal

PCI device requires it.

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