MPC8555CPXAPF datasheet(36/88 Pages) FREESCALE

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MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Local Bus

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for

clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the

output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for DLL enabled mode.

3. All signals are measured from OVDD/2 of the rising edge of local bus clock for DLL bypass mode to 0.4 × OVDD of the signal

in question for 3.3-V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

6. The value of tLBOTOT is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local

bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at OVDD/2.

8. Guaranteed by characterization.

9. Guaranteed by design.

Figure 15 provides the AC test load for the local bus.

Figure 15. Local Bus C Test Load

Local bus clock to address valid for LAD

LWE[0:1] = 00

tLBKLOV3

—0.8

LWE[0:1] = 11 (default)

2.3

Output hold from local bus clock (except

LAD/LDP and LALE)

LWE[0:1] = 00

tLBKLOX1

-2.7

—

LWE[0:1] = 11 (default)

-1.8

Output hold from local bus clock for

LAD/LDP

LWE[0:1] = 00

tLBKLOX2

-2.7

—

LWE[0:1] = 11 (default)

-1.8

Local bus clock to output high Impedance

(except LAD/LDP and LALE)

LWE[0:1] = 00

tLBKLOZ1

—1.0

LWE[0:1] = 11 (default)

2.4

Local bus clock to output high impedance

for LAD/LDP

LWE[0:1] = 00

tLBKLOZ2

—1.0

LWE[0:1] = 11 (default)

2.4

Table 31. Local Bus General Timing Parameters - DLL Bypassed (continued)

Parameter

Configuration 7

Symbol 1

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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