MPC8555CPXAPF datasheet(34/88 Pages) FREESCALE

номер детали	MPC8555CPXAPF

подробное описание детали	PowerQUICC??III Integrated Communications Processor Hardware Specifications

PDF	88 Pages

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производитель	FREESCALE [Freescale Semiconductor, Inc]

домашняя страница	http://www.freescale.com

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MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Local Bus

9.2

Local Bus AC Electrical Specifications

Table 30 describes the general timing parameters of the local bus interface of the MPC8555E with the DLL

enabled.

Table 30. Local Bus General Timing Parameters - DLL Enabled

Parameter

Configuration 7

Symbol 1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

6.0

—

LCLK[n] skew to LCLK[m] or LSYNC_OUT

tLBKSKEW

—

150

7, 9

Input setup to local bus clock (except

LUPWAIT)

tLBIVKH1

1.8

—

3, 4, 8

LUPWAIT input setup to local bus clock

tLBIVKH2

1.7

—

3, 4

Input hold from local bus clock (except

LUPWAIT)

tLBIXKH1

0.5

—

3, 4, 8

LUPWAIT input hold from local bus clock

tLBIXKH2

1.0

—

3, 4

LALE output transition to LAD/LDP output

transition (LATCH hold time)

tLBOTOT

1.5

—

Local bus clock to output valid (except

LAD/LDP and LALE)

LWE[0:1] = 00

tLBKHOV1

—

2.3

3, 8

LWE[0:1] = 11 (default)

3.8

Local bus clock to data valid for LAD/LDP

LWE[0:1] = 00

tLBKHOV2

—

2.5

3, 8

LWE[0:1] = 11 (default)

4.0

Local bus clock to address valid for LAD

LWE[0:1] = 00

tLBKHOV3

—

2.6

3, 8

LWE[0:1] = 11 (default)

4.1

Output hold from local bus clock (except

LAD/LDP and LALE)

LWE[0:1] = 00

tLBKHOX1

0.7

—

3, 8

LWE[0:1] = 11 (default)

1.6

Output hold from local bus clock for

LAD/LDP

LWE[0:1] = 00

tLBKHOX2

0.7

—

3, 8

LWE[0:1] = 11 (default)

1.6

Local bus clock to output high Impedance

(except LAD/LDP and LALE)

LWE[0:1] = 00

tLBKHOZ1

—

2.8

5, 9

LWE[0:1] = 11 (default)

4.2

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