33989 datasheet(43/66 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33989

TYPICAL APPLICATIONS

SUPPLEMENTAL APPLICATION NOTES

Figure 27. CAN Wake-Up

• T1(third valid CAN dominant pulse to VDD1 turn on): typ

80 µs.

• T2 and T3 identical to page 39 above

• The total time is 6.58 ms in this example.

LX with Cyclic Sense

The case below is a description of the wake-up by LX input

associated with the cyclic sense function.

Figure 28.

• T1: Is dependent on the selected cyclic sense timing in

the TIM2 register (5 ms to 400 ms). LX is sampled

•10 µs before the end of cyclic sense on time. If the LX

correct wake-up level happens just after the sample

• point, the wake-up will be detected at the next HS1

activation and a complete period is lost.

• T2: It is the same time as LX to VDD1 turn on: typ

100 µs

• T3 & T4: same as page 39

• The total time is 11.5 ms (for a cyclic sense total time of

5 ms) in this example.

WAKE-UP TIMING: STOP MODE

The following paragraphs describe the wake-up events

from stop mode, and the sequence of the signals at the SBC

level. The wake-up time described is the time from the wake-

up event to the SBC INT pin. The wake-up time is the sum of

several timings: wake-up signal detection, the INT pulse, and

a minimum delay between INT and SBC ready to operate. At

the end of the wake-up time, the SBC is ready to operate,

however the MCU might have already been in a restart

operation.

LX Wake-Up

Below is the case where the SBC is in stop mode and is

awakened by an LX positive edge

• T1(L0 high level to INT pulse): typ 100 µs.

• The total time is 133 µs in this case.

CAN

VDD1

RESET

tCAN

RST

VDD1

RESET

HS1

RST

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