33989 datasheet(37/66 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33989

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Interrupt Register (INT)

This register allows masking or enabling the interrupt

source. A read operation informs about the interrupt source.

When the mask bit is set, INT pin goes low if the

appropriate condition occurs.

If HS1OT - V2LOW interrupt is only selected (only bit D2 set

in INT register), reading INT register bit D2 leads to two

possibilities:

1. Bit D2 = 1: INT source is HS1OT

2. Bit D2 = 0: INT source is V2LOW

HS1OT and V2LOW bits status are available in IOR.

Upon a wake-up condition from Stop mode due to over

current detection (IDD1SW-U1 or IDD1S-WU2), an INT pulse is

generated; however, INT register content remains at 0000

(not bit set into the INT register).

The status bit of the INT register content is a copy of the

IOR and CAN registers status content. To clear the INT

(read register). Once this operation is done at IOR and CAN

Errors bits are latched in the CAN register and IOR.

Table 31. INT Register

INT

$111B

VSUPLOW

HS1OT-V2LOW

VDDTEMP

CANF

VSUPLOW

HS1OT

VDDTEMP

CANF

Reset Value

Reset Condition

POR, RST

Table 32. INT Control Bits

Control Bit

Description

CANF

Mask Bit for CAN Failures

VDDTEMP

Mask Bit for VDD Medium Temperature (Pre-Warning)

HS1OT - V2LOW

Mask Bit for HS1 Over Temperature AND V2 Below 4.0 V

VSUPLOW

Mask Bit for VSUP Below 6.1 V

Table 33. INT Status Bits

Status Bit

Description

CANF

CAN Failure

VDDTEMP

VDD Medium Temperature (pre-warning)

HS1OT

HS1 Over Temperature

VSUPLOW

VSUP Below 6.1 V

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