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LR4102 датащи(PDF) 5 Page - LSI Computer Systems |
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LR4102 датащи(HTML) 5 Page - LSI Computer Systems |
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5 / 32 page ![]() TinyRISC LR4102 Microprocessor 5 Instruction Set Summary Table 1 summarizes the 32-bit instruction set for the LR4102, and Table 2 lists the unimplemented MIPS II instructions. Table 3 provides a summary of the LR4102 MIPS16 instruction set. Table 1 LR4102 32-Bit Instruction Set Summary Load and Store Instructions LB Load Byte SB Store Byte LBU Load Byte Unsigned SH Store Halfword LH Load Halfword SW Store Word LHU Load Halfword Unsigned SWL Store Word Left LW Load Word SWR Store Word Right LWL Load Word Left SYNC Synchronize (load/store synchronization) LWR Load Word Right – – Arithmetic Instructions: ALU Immediate ADDI Add Immediate ORI OR Immediate ADDIU Add Immediate Unsigned SLTI Set on Less Than Immediate ANDI AND Immediate SLTIU Set on Less Than Immediate Unsigned LUI Load Upper Immediate XORI Exclusive OR Immediate Arithmetic Instructions: Three-Operand, Register-Type ADD Add SLT Set on Less Than ADDU Add Unsigned SLTU Set on Less Than Unsigned AND Logical AND SUB Subtract NOR Logical NOR SUBU Subtract Unsigned OR Logical OR XOR Logical Exclusive OR (Sheet 1 of 4) |
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