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LR4102 датащи(PDF) 3 Page - LSI Computer Systems

номер детали LR4102
подробное описание детали  Microprocessor
PDF  32 Pages
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производитель  LSI [LSI Computer Systems]
домашняя страница  http://www.lsicsi.com
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LR4102 датащи(HTML) 3 Page - LSI Computer Systems

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TinyRISC LR4102 Microprocessor
3
Block Diagram
This section provides short descriptions of the major components of the
LR4102, as shown in Figure 1.
The CPU performs all arithmetic, logical, shift, and address calculations.
The CPU supports EJTAG debug and is closely coupled with the
FastMDU. The FastMDU calculates all multiply and divide operations for
the LR4102, and provides 4/5 cycle multiply and accumulate operations
(32 bit to 64 bit), 34/35 cycle divide, saturated math, and overflow
indication.
The memory management unit (MMU) translates virtual addresses from
the CPU into physical addresses and includes a 64-entry translation
look-aside buffer (TLB) RAM.
The BIU and cache controller (BBCC) provides an internal bus interface
and connects the CPU to the caches. For the caches, the LR4102
contains 16 Kbytes of two-way set-associative I-Cache and 8 Kbytes of
direct-mapped D-Cache. Four Write Buffers are integrated with the
BBCC in the LR4102 design.
The 32-bit FBusMACRO (FBM) controls the FBus, a dedicated,
multimaster bus that connects off-chip logic with the LR4102. The FBus
allows seamless LR4102 connection to a variety of devices, including
EPROM, FLASH, RAM, DRAM, SDRAM, and general-purpose I/O pins.
The FBus also supports burst read (one cycle) and write, built-in
arbitration for an external FBus master, and snooping of external write
accesses to memory. Internally, the FBusMACRO interfaces mainly with
the BBCC module.
Each 32-bit Timer can count down from a preloaded value, roll over or
stop at zero, generate an interrupt on zero, or act as bus watchdog. The
CPU can program either of the two internal 32-bit timers.
The LR4102 includes 1 Kbyte of on-chip memory (OCM).
The Clock Controller steps CPU clock speed up or down, and can stop
the internal LR4102 clock altogether. The LR4102 also supports a low
power mode. The LR4102 Clock Controller is designed to support a
crystal or canned oscillator, and has an on-chip PLL for frequency
multiplication.



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