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LR4102 датащи(PDF) 22 Page - LSI Computer Systems |
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LR4102 датащи(HTML) 22 Page - LSI Computer Systems |
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22 / 32 page ![]() 22 TinyRISC LR4102 Microprocessor T1_OUTN2 2.7 8.9 ns TRDYN 0.8 7.2 ns 1. With 65 pF load 2. This signal is related to the system clock, but not to the FAPI bus (see Figure 5 note). 3. This signal is related to both the system clock and the FAPI bus (see Figure 5 note). Table 12 AC Output Timing with respect to rising edge of SDCLKP1 1. With 65 pF load. Output Signal1 Min Max Units FADDRP[28:0] 1.7 6.9 ns FADP[31:0] 1.2 8.3 ns SD_CASN[3:0]_DMP[3:0] 1.7 6.9 ns SD_OEN_CASN 1.8 6.6 ns SD_RASN 1.7 6.4 ns SD_RASN[1:0]_CSN[1:0] 1.7 6.8 ns SD_WEN_WEN 1.8 6.6 ns Table 13 AC Output Timing with respect to falling edge of TCK Output Signal1 1. With 65 pF load Min Max Units TDO_TPC 2.1 8.9 ns Table 11 AC Output Timing with respect to rising edge of PBCLKP1 (Cont.) Output Signal1 Min Max Units (Sheet 2 of 2) |
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