Preliminary Technical Data

AD5522

Rev. PrM | Page 11 of 48

SCLK

SYNC

SDI

SDO

29

58

DB28

DB0

DB23/

DB28

DB0

DB0

INPUT WORD SPECIFIES

REGISTER TO BE READ

UNDEFINED

NOP CONDITION

SELECTED REGISTER DATA

CLOCKED OUT

DB23/

DB28

Figure 6. SPI Read Timing (Readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges)

SYNC

SYNC

SCLK

SDI

SDI

SCLK

MSB

D28

LSB

D0

t6

t1

t2

t3

t4

t5

SDO

LSB

D0

MSB

D23/D28

t7

SELECTED REGISTER DATA CLOCK OUT

UNDEFINED

MSB

DB23/

DB28

LSB

DB0

SDO

t8

Figure 7. LVDS Read and Write Timing, (Readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges)