Preliminary Technical Data

AD5522

Rev. PrM | Page 37 of 48

READ REGISTERS

Readback of all the registers in the device is possible via the both SPI and LVDS interfaces. In order to readback data from a register, it is

first necessary to write a “readback” command to tell the device which register is required to readback. See Table 22 to address the

appropriate channel.

Table 22. Read Functions of the AD5522

B28

B27

B26

B25

B24

B23

B22

B21 to B0

SELECTED REGISTER

RD/WR

PMU3

PMU2

PMU1

PMU0

MODE1

MODE0

DATA BITS

CH3

CH2

CH1

CH0

READ FUNCTIONS

1

0

0

0

0

0

0

All zeros

Read from System Control Register

1

0

0

0

0

0

1

All zeros

Read from Comparator Status Registers

1

0

0

0

0

1

0

X

Reserved

1

0

0

0

0

1

1

All zeros

Read from Alarm Status Register

READ ADDRESSED PMU REGISTER – ONLY ONE PMU REGISTER CAN BE READ AT ONE TIME

1

0

0

0

1

0

0

×

×

×

CH0

1

0

0

1

0

0

0

×

×

CH1

×

1

0

1

0

0

0

0

×

CH2

×

×

1

1

0

0

0

0

0

All zeros

CH3

×

×

×

READ ADDRESSED DAC “m” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME

1

0

0

0

1

0

1

×

×

×

CH0

1

0

0

1

0

0

1

×

×

CH1

×

1

0

1

0

0

0

1

×

CH2

×

×

1

1

0

0

0

0

1

DAC ADDRESS

SEE

Table 21

CH3

×

×

×

READ ADDRESSED DAC “c” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME

1

0

0

0

1

1

0

×

×

×

CH0

1

0

0

1

0

1

0

×

×

CH1

×

1

0

1

0

0

1

0

×

CH2

×

×

1

1

0

0

0

1

0

DAC ADDRESS

SEE

Table 21

CH3

×

×

×

READ ADDRESSED DAC “x1” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME

1

0

0

0

1

1

1

×

×

×

CH0

1

0

0

1

0

1

1

×

×

CH1

×

1

0

1

0

0

1

1

×

CH2

×

×

1

1

0

0

0

1

1

DAC ADDRESS

SEE

Table 21

CH3

×

×

×

Once the required channel has been addressed, the device will load the 24 bit Readback data into the MSB positions of the 29 Bit serial

shift register, the five LSB bits will be filled with zeros. SCLK rising edges clock this readback data out on SDO(framed by the SYNC

signal).

A minimum of 24 clock rising edges are required to shift the readback data out of the shift register. If writing a 24-bit word to shift data

out of the device, user must ensure that the 24 bit write is effectively a NOP (No Operation) command. The last 5 bits in the shift register

will always be 00000b, these five bits will become the MSBs of the shift register when the 24 bit write is loaded. To ensure the device

receives a NOP command as outlined in Table 14, the recommended flush command is 0xFFFFFF and no change will be made to any

register within the device.

Readback data may also be shifted out by writing another 29 bit write or read command. If writing a 29-bit command, the readback data

will be MSB data available on SDO, followed by 00000b.