33889 datasheet(37/60 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33889

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 16. Simplified State Machine

Sleep

VDD1: OFF

V2: OFF

HS1 OFF or cyclic

CAN (always enable

SPI and L0,L1

Cyclic sense

Forced Wake-up

Low

Not active

No Running

Term Vbat.

Table 7. 33889 Table of Operations

The table below describe the SBC operation modes.

MODE

VOLTAGE

REGULATOR

HS1 SWITCH

WAKE-UP

CAPABILITIES

(IF ENABLED)

RESET PIN

INT

SOFTWARE

WATCHDOG

CAN CELL

State Machine (not valid in debug modes)

Power

Down

Reset

Normal Request

Standby

Stop

Normal

Sleep

Reset

counter

(1 ms) expired

VDD1 low OR W/D: time

out 350 ms & !Nostop

SPI: standby &

W/D

trigger

(note1)

SPI: Stop &

low

high

transition

W/D: timeout OR VDD1 low

W/D: timeout & Nostop & !BATFAIL

W/D: timeout OR VDD1 low

: tim

ut O

low

(no

te2

)

Wake-up

(VDD1 high temperature OR (VDDd1 low > 100 ms & VSUP >BFew)) & Nostop & !BATFAIL

4 denotes priority

State machine description:

“Nostop” means Nostop bit = 1

“! Nostop” means Nostop bit = 0

“BATFAIL” means Batfail bit = 1

“! BATFAIL” means Batfail bit = 0

“VDD1 over temperature” means VDD1 thermal shutdown occurs

“VDD1 low” means VDD1 below reset threshold

“VDD1 low > 100 ms” means VDD1 below reset threshold for more than

100 ms

“W/D: Trigger” means TIM1 register write operation.

VSUP > BFew means VSUP > Battery Fall Early Warning (6.1 V typical)

“W/D: timeout” means TIM1 register not written before W/D timeout period

expired, or W/D written in incorrect time window if window W/D selected

(except stop mode). In normal request mode timeout is 355 ms p2.2 (350 ms

p3)ms.

“SPI: Sleep” means SPI write command to MCR register, data sleep

“SPI: Stop” means SPI write command to MCR register, data stop

“SPI: Normal” means SPI write command to MCR register, data normal

“SPI: Standby” means SPI write command to MCR register, data standby

Note 1: these 2 SPI commands must be send in this sequence and

consecutively.

Note 2: if W/D activated

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