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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TSL2568CS датащи(PDF) 31 Page - OSRAM GmbH |
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TSL2568CS датащи(HTML) 31 Page - OSRAM GmbH |
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31 / 56 page  Page 30 ams Datasheet Document Feedback [v1-00] 2016-Apr-12 TSL2568, TSL2569 − Principles of Operation ADC Channel Data Registers (Ch − Fh) The ADC channel data are expressed as 16-bit values spread across two registers. The ADC channel 0 data registers, DATA0LOW and DATA0HIGH provide the lower and upper bytes, respectively, of the ADC value of channel 0. Registers DATA1LOW and DATA1HIGH provide the lower and upper bytes, respectively, of the ADC value of channel 1. All channel data registers are read-only and default to 00h on power up. Figure 37: ADC Channel Data Registers The upper byte data registers can only be read following a read to the corresponding lower byte register. When the lower byte register is read, the upper eight bits are strobed into a shadow register, which is read by a subsequent read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles end between the reading of the lower and upper registers. Note(s): The Read Word protocol can be used to read byte-paired registers. For example, the DATA0LOW and DATA0HIGH registers (as well as the DATA1LOW and DATA1HIGH registers) may be read together to obtain the 16-bit ADC value in a single transaction. Register Address Bits Description DATA0LOW Ch 7:0 ADC channel 0 lower byte DATA0HIGH Dh 7:0 ADC channel 0 upper byte DATA1LOW Eh 7:0 ADC channel 1 lower byte DATA1HIGH Fh 7:0 ADC channel 1 upper byte |
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