TSL2568CS datasheet(28/56 Pages) OSRAM

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ams Datasheet

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[v1-00] 2016-Apr-12

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TSL2568, TSL2569 − Principles of Operation

When a level Interrupt is selected, an interrupt is generated

whenever the last conversion results in a value outside of the

programmed threshold window. The interrupt is active-low and

remains asserted until cleared by writing the Command

In SMBAlert mode, the interrupt is similar to the traditional level

style and the interrupt line is asserted low. To clear the interrupt,

the host responds to the SMBAlert by performing a modified

Receive Byte operation, in which the Alert Response Address

(ARA) is placed in the slave address field, and the TSL256x that

generated the interrupt responds by returning its own address

in the seven most significant bits of the receive data byte. If

more than one device connected on the bus has pulled the

SMBAlert line low, the highest priority (lowest address) device

will win communication rights via standard arbitration during

the slave address transfer. If the device loses this arbitration,

the interrupt will not be cleared. The Alert Response Address is

0Ch.

When INTR = 11, the interrupt is generated immediately

following the SMBus write operation. Operation then behaves

in an SMBAlert mode, and the software set interrupt may be

cleared by an SMBAlert cycle.

Note(s): Interrupts are based on the value of Channel 0 only.

Figure 33:

Interrupt Control Register

5432

Resv

INTR

PERSIST

Field

Bits

Description

Resv

7:6

Reserved. Write as 0.

INTR

5:4

INTR Control Select. This field determines mode of interrupt logic according to

Figure 34, below.

PERSIST

3:0

Interrupt persistence. Controls rate of interrupts to the host processor as shown in

Figure 35, below.

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