TMD2621 datasheet(28/59 Pages) OSRAM

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Datasheet, Public

Page 27

[v4-00] 2023-Apr-12

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TMD2621 − Register Overview

All flags with access type of RW, SC in STATUS and STATUS_2

registers can be cleared by setting the bit high. Alternatively, if

the INT_READ_CLEAR in the CFG3 register bit is set, then simply

reading this register automatically clears all flags.

CFG2 Register (Address 0xA7)

Figure 40:

CFG2 Register

5PWINT

RW, SC

This flag is set when PWTIME is completed if PWIEN =1.

This flag is set only in parallel/concurrent mode and only

when PWEN = 1.

Reserved

RW, SC

Reserved. Must be set to default value.

PSAT_1STG_AMB

RW, SC

This flag indicates proximity saturation is from first stage

of proximity engine due to ambient in subtraction

phase.

PSAT_1STG_

PULSE

0RW, SC

This flag indicates proximity saturation is from first stage

of proximity engine when VCSEL pulse is emitted.

VSYNC_LOST_INT

RW, SC

Interrupt when VSYNC watchdog timeout happens or

internal oscillator is stopped e.g PON=0. This interrupt

generated on event based.

VSYNC_CHG_INT

RW, SC

Interrupt when there is a change in VSYNC period.

Addr: 0xA7

CFG2

Bit

Bit Name

Default

Access

Bit Description

7:2

Reserved

Reserved. Must be set to default value.

SKIP_IDAC_SAR

If set, the IDAC_SAR is skipped.

0DISABLE_IDAC

If set, the IDAC is disabled.

If SKIP_IDAC_SAR =DISABLE_IDAC =0, it enables the

IDAC to automatically remove most of the ambient IR

light to avoid a saturation caused by high ambient IR

components. The function runs before every PTIME,

and the time required is given by the formula: prox_

init_time =7 x (PPULSE_LEN +42.15μs).

Addr: 0xA1

STATUS_2

Bit

Bit Name

Default

Access

Bit Description

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