TMD2621 datasheet(18/59 Pages) OSRAM

18 / 59 page

Datasheet, Public

Page 17

[v4-00] 2023-Apr-12

Document Feedback

TMD2621 − Register Overview

PTIME Register (Address 0x82)

Figure 21:

PTIME Register

PILTL Register (Address 0x88)

Figure 22:

PILTL Register

PILTH Register (Address 0x89)

Figure 23:

PILTH Register

The contents of the PILTH and PILTL registers are combined and

treated as a fourteen (14) bit threshold low value. If the value

generated by the proximity ADC (PDATA) is below the PILTL/H

threshold and the PPERS value is reached, then the low

proximity threshold is breached. When setting the 14-bit

proximity threshold, PILTL must be written first, immediately

follow by PILTH. Internally, the lower 8 bits are buffered until

Addr: 0x82

PTIME

Bit

Bit Name

Default

Access

Bit Description

7:0

PTIME

0x1F

This register defines the duration of 1 Prox Sample,

which is (PTIME + 1)*88μs. PTIME needs to be

programmed greater than proximity integration time,

otherwise it's ignored.

Addr: 0x88

PILTL

Bit

Bit Name

Default

Access

Bit Description

7:0

PILTL

0x00

This register contains the low byte of the 14-bit

proximity LOW threshold when APC is enabled. If APC

is disabled, this register contains the LOW threshold

which is an 8-bit value which is compared against the

upper 8 bits of the 10-bit proximity value.

Addr: 0x89

PILTH

Bit

Bit Name

Default

Access

Bit Description

7:6

Reserved

Reserved. Must be set to default value.

5:0

PILTH

000000

This register contains the upper 6 bits of the 14-bit

proximity LOW threshold when APC is enabled. If APC

is disabled, this register is ignored.

TMD2621 датащи(PDF) 18 Page - OSRAM GmbH

TMD2621 датащи(HTML) 18 Page - OSRAM GmbH

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

датащи скачать

ссылки URL