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AS7331

Functional Description

Datasheet

• PUBLIC

DS001047

• v4-00 • 2023-Mar-24

│ 41

Figure 35:

Relation of the Measurement Result to the Conversion Time with Enabled and Set Divider

7.6

Conversion Time Measurement in SYND Mode

In the case of SYND measurement mode, the conversion time is fully controlled by the external signal

at the SYN pin. The relative deviation of this time to the internal clock frequency2 can produce some

deviations in the conversion result. However, this time can be measured in time units of the internal

system clock extended up to 24 bits. It allows for the recalculation of the measured input light more

precisely (see chapter 7.4). Furthermore, the measurement result can be compensated for any

deviation, which can occur in the clock frequency due to temperature or supply voltage variations. The

conversion time measurement can be enabled by setting bit CREG2:EN_TM bit to

“1” (see Figure 49).

At the end of the conversion, the result is stored into the output register, OUTCONV, (see Figure 54)

synchronously with the measurement results (MRES).

The stored value follows the relation:

Equation 6:

CLK

CONV

OUTCONV





The bit STATUS:OUTCONVOF of the status register (see Figure 55) shows an overflow of the

conversion time counter, OUTCONV. In case it happens and the conversion is still in process, the

counter, OUTCONV, starts again at 0. For the calculation of the full-scale range (FSR) see Equation 2,

Equation 3, Equation 4 in chapter 7.4.

7.7

Temperature Measurement

In addition to the three optical channels, a temperature measurement is done in parallel. The

measurement result is available as TEMP of the output result registers. The resolution of the

temperature measurement is 12 bits by a step size of 0.05 K per bit, which means 20 counts per

Kelvin. The value of the chip temperature (silicon

– measured in °C) is equal to:

2 The system clock is internally generated and is subject to technological tolerances, which means that clock frequencies of

different devices may vary.

12 11 10 9 8 7 6 5 4 3 2

19 18 17 16 15 14 13

23 22 21

12 11 10 9 8 7 6 5 4 3 2

15 14 13

OUTCONV

MRES

CREG2:EN_DIV = ‚1'

CREG2:DIV = 2 dec

DIV = 7 … 2 … 0

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