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AS7331

Datasheet

• PUBLIC

DS001047

• v4-00 • 2023-Mar-24

│ 57

Figure 52:

EDGES Register

Addr: Ah

EDGES

Bit

Bit Name

Default

Access

Bit Description

7:0

EDGES

01h

Value [dec]

Function

1…255

Number of SYN falling

edges.

8.2.8

Option Register - OPTREG (Address Bh)

The register bit OPTREG:INIT_IDX allows to communicate via the I²C with simple masters, which do

not support the I²C repeated START condition. In this case, the start address for a read operation can

only be set by complete write access with the I²C STOP condition at the end. For this kind of simple

I²C master

, the bit INIT_IDX has to be “0”. Then, the reading of data starts at the given index address.

After each data transfer, the index address is incremented.

With INIT_IDX set to “1”, each short read operation starts at the default address 2h in Measurement

mode and 0h in Configuration mode. The setting of the internal read index address followed by the I²C

repeated START condition, works as usual. After each data transfer, the index address is

incremented. Please also see chapter 7.8.4.

Figure 53:

Option Register

Addr: Bh

OPTREG

Bit

Bit Name

Default [b]

Access

Bit Description

7:1

0111001

Reserved

(Default value after power-on reset and

software reset, but different, irrelevant

values after changing CREG1:GAIN or

CREG3:CCLK. The recommended write

value is 0000000b in case of

OPTREG:INIT_IDX should be changed.)

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