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AS7331

Datasheet

• PUBLIC

DS001047

• v4-00 • 2023-Mar-24

│ 56

to one READY line with a pull-up resistor. As long as one device still measures, the READY line is

active low.

The internal clock frequency fCLK, is controlled by the bits of CREG3:CCLK. Higher clock rates result in

shorter conversion times for the measurement. However take care of CREG1:GAIN

– with higher

frequencies than 1 MHz, in some cases, the irradiance responsivity is reduced (see Figure 33).

8.2.6

BREAK Register (Address 9h)

The register BREAK defines the time between two consecutive measurements of CONT, SYNS, and

SYND modes.

Figure 51:

BREAK Register

Addr: 9h

BREAK

Bit

Bit Name

Default

Access

Bit Description

7:0

BREAK

19h

Value [dec]

Function

0…255

Break time TBREAK

between two

measurements (except

CMD mode): from 0 to

2040

μs, step size

μs.

The value 0h results in

a minimum time of 3

clocks of fCLK.

8.2.7

EDGES Register (Address Ah)

The register EDGES becomes operative in SYND mode. After a measurement was started in SYND

mode, it defines the necessary number of additional falling edges at input SYN until the conversion is

termi

nated. The value EDGES = “0” is not allowed and results in the initial value “1”.

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