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AS73211

Datasheet

• PUBLIC

DS000556

• v3-01 • 2018-Feb-07

│ 49

Figure 49:

Configuration Register 2 (CREG2)

– Address 7h

CREG2

NAME

VALUE [b]

CONFIGURATION

bit 7

Reserved (1)

bit 6

EN_TM

In combination with SYND mode the internal

measurement of the conversion time is disabled and no

temperature measurement takes place.

1 (2)

Internal measurement of the externally defined conversion

time via SYN pulse in SYND mode is enabled (OUTCONV

results are generated as well as temperature values for

output register TEMP).

bit 5 to 4

Reserved (1)

bit 3

EN_DIV

0 (2)

Digital divider of the measurement result registers is

disabled

Digital divider of the measurement result registers is

enabled (might be needed @ CREG1:TIME > 6 dec)

bit 2 to 0

DIV

Value of the divider (21+DIV[dec])

000 (2)

001

010

011

100

101

110

111

(1)

The default value after power-

on reset and software reset is ,0‘ as well as the recommended write value.

(2)

Default value after power-on reset and software reset.

In SYND mode, the conversion time is externally controlled via pin SYN. In that case the bit

CREG2:EN_TM enables the counting of internal clocks within the external given conversion time as

well as the access to the output register OUTCONV, which contains the counting result. It is possible

to count a number of clocks up to 24 bits. In case of this function is not used in SYND mode (equal to

CREG2:EN_TM = ,0

‘) no result for temperature measurement is generated. The values for output

The bit CREG2:EN_DIV enables the internal prescaler, which could be interesting for conversion

times more than 16 bits

(CREG1:TIME ≥ 0111b) and in case of SYND mode is used. The value of

CREG2:DIV is only valid with CREG2:EN_DIV = ,1

‘. Then the measurement range is extended while

the resolution of the 16-bit register results is reduced at the same time (see Divider). Thus it is also

possible to generate complete measurement results for conversion times from 217 to 224 system clocks

(CREG1:TIME). If the chosen value of the prescaler is too small, a counter overflow could occur,

which is shown by the bit STATUS:MRESOF of the result register bank.

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