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AS73211

Functional Description

Datasheet

• PUBLIC

DS000556

• v3-01 • 2018-Feb-07

│ 36

In the SYND mode, the maximum value of the conversion result depends on the external controlled

conversion time. This maximum achievable count is equal to OUTCONV and differs from the full-scale

count achievable in CMD, CONT and SYNS mode.

The value of CREG1:TIME defines the number of clock counts during the conversion time. It defines

the conversion time duration and maximal resolution of the A/D conversion. This is valid for the CONT,

CMD and SYNS mode.

In the SYND mode the value of CREG1:TIME does not have any meaning for the conversion time

duration, because this time is externally defined.

For values of CREG1:TIME higher than 6dec (0110b) TCONV becomes bigger than 216, which results in

A/D conversions with a higher resolution starting from 17 bit up to 24 bit. Only the least 16 significant

bits are further processed and stored in the result registers. Using the implemented divider (see

chapter

”Divider”) helps to access the upper 8 bits, too.

The value of CREG1:GAIN defines the A/D converter’s gain (see Figure 48 and FSR values in Figure

29 to Figure 34

), which determines the sensor’s irradiance responsivity Re. The values of

CREG1:GAIN of the referred tables are only valid for a clock frequency fCLK of 1MHz. For higher clock

frequencies, some gain increments are not accessible. Figure 45 shows the valid gains in dependency

of the chosen internal system clock via CREG3:CCLK.

Figure 35:

Achievable GAIN for Different Internal Clock Frequencies Chosen by CREG3:CCLK

CREG3:CCLK

[dec]

fCLK [MHz]

1.024

2.048

4.096

8.192

CREG1:GAIN [dec]

adjustable GAIN

2048x

1024x

512x

256x

1024x

512x

256x

128x

64x

32x

16x

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