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AS73211

Functional Description

Datasheet

• PUBLIC

DS000556

• v3-01 • 2018-Feb-07

│ 40

I²C (pins SCL and SDA) should be considered, especially regarding to noise environments and EMC

in PCB design. For the I²C interface timing diagram and its timing specification please see Figure 7 .

Clock stretching is not supported by the AS73211. I²C commands towards AS73211 takes effect after

the end of the I²C write cycle (I²C Stop condition).

Each data transfer begins with a start (S) condition, defined by a high to low transition of SDA while

SCL is high. The transfer is terminated by a stop (P) condition, which is defined by a low to high

transition of SDA while SCL is high. A repeated start condition (Sr) can be generated instead of a stop

condition, if the transfer should be continued with a new data block. The start and repeated start

condition are functionally equivalent.

Figure 38:

Start and Stop Conditions of the I²C Bus

After the protocol started, the data at pin SDA must be stable as long as the high phase of I²C clock at

pin SCL takes. The change of the communication data at pin SDA is only allowed during the low

phase of SCL clock.

Figure 39:

Bit

– Transfer on I²C Bus

Each data transfer consists of 1 byte, which has to be followed by an acknowledge bit (A) (see Figure

40). The bits arrive with the MSB first. The acknowledge signal shall be pulled low by the receiver

during the high period of the ninth clock pulse while the transmitter releases the SDA line. When SDA

stays high during the ninth clock pulse the not acknowledge signal (NA) is output. After the not

acknowledge signal the master generates either a stop or a repeated start condition depending on

whether the master either wants to abort or start a new transfer. In case of the AS73211 as slave a not

acknowledge (NA) is only generated if the device address did not match.

SDA

SCL

S = START

condition

Sr = repeated START

condition

P = STOP

condition

SCL

SDA

data line

stable;

data valid

change

of data

allowed

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