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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PCK2010DL датащи(PDF) 2 Page - NXP Semiconductors |
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PCK2010DL датащи(HTML) 2 Page - NXP Semiconductors |
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2 / 16 page  Philips Semiconductors Preliminary specification PCK2010 CK98 (100/133MHz) Spread Spectrum System Clock Generator 2 1999 Mar 01 FEATURES • Mixed 2.5V and 3.3V operation • Four CPU clocks at 2.5V • Eight PCI clocks at 3.3V, one free-running (synchronous with CPU clocks) • Four 3.3V fixed clocks @ 66MHz • Two 2.5V CPUDIV2 clocks @ ½ CPU clock frequency • Three 2.5V IOAPIC clocks @ 16.67 MHz • One 3.3V 48MHz USB clock • Two 3.3V reference clocks @ 14.318 MHz • Reference 14.31818 MHz Xtal oscillator input • 133 MHz or 100 MHz operation • Power management control input pins • LOW CPU clock jitter ≤ 250 ps cycle-cycle • LOW skew outputs • 0.0ns – 1.5ns CPU - 3V66 delay • 1.5ns – 4.0ns 3V66 - PCI delay • 1.5ns – 4.0 ns CPU - IOAPIC delay • Available in 56-pin SSOP package • ±0.5% center spread spectrum capability via select pins; –0.5% down spread spectrum capability via select pins DESCRIPTION The PCK2010 is a clock synthesizer/driver chip for a PentiumII and other similar processors. The PCK2010 has four CPU clock outputs at 2.5V, two CPUDIV2 clock outputs running at ½ CPU clock frequency (66MHz or 50MHz depending on the state of SEL133/100) and four 3V66 clocks running at 66MHz. There are eight PCI clock outputs running at 33MHz. One of the PCI clock outputs is free-running. Additionally, the part has three 2.5V IOAPIC clock outputs at 16.67MHz and two 3.3V reference clock outputs at 14.318MHz. All clock outputs meet Intel’s drive strength, rise/fall time, jitter, accuracy, and skew requirements. The part possesses dedicated power-down, CPUSTOP, and PCISTOP input pins for power management control. These inputs are synchronized on-chip and ensure glitch-free output transitions. When the CPUSTOP input is asserted, the CPU clock outputs and 3V66 clock outputs are driven LOW. When the PCISTOP input is asserted, the PCI clock outputs are driven LOW. Finally, when the PWRDWN input pin is asserted, the internal reference oscillator and PLLs are shut down, and all outputs are driven LOW. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 27 28 30 29 VSS REF0 REF1 VDD3V XTAL_IN XTAL_OUT PCICLK_F PCICLK1 VDD3V PCICLK2 PCICLK3 VSS PCICLK4 PCICLK5 PCICLK6 PCICLK7 VSS VSS VDD3V VSS 3V66_0 VDD3V VSS 3V66_3 3V66_1 3V66_2 VDD3V SEL133/100 VDD25V APIC2 APIC1 APIC0 VSS VDD25V CPUDIV2_0 VSS VDD25V CPUCLK1 CPUCLK0 VSS VDD3V VSS CPUSTOP PWRDWN SPREAD CPUDIV2_1 PCISTOP CPUCLK3 CPUCLK2 VDD25V SEL1 VDD3V VSS SEL0 48MHz VSS SW00352 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DRAWING NUMBER 56-Pin Plastic SSOP 0 °C to +70°C PCK2010 DL PCK2010 DL SOT371-1 Intel and Pentium are registered trademarks of Intel Corporation. |
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