Philips Semiconductors

Preliminary specification

PCK2010

CK98 (100/133MHz) Spread Spectrum System Clock

Generator

1999 Mar 01

5

168-pin SDR SDRAM DIMM

The PLL clock distribution device and SSTL registered drivers reduce

signal loads on the memory controller and prevent timing delays and

waveform distortions that would cause unreliable operation

AVC

PCK2509S or PCK2510S

AVC

BACK SIDE

FRONT SIDE

AVC

SW00403

FUNCTION TABLE

SEL

133/100

SEL1

SEL0

CPU

CPUDIV2

3V66

PCI

48MHz

REF

IOAPIC

NOTES

0

0

0

HI-Z

HI-Z

HI-Z

HI-Z

HI-Z

HI-Z

HI-Z

1

0

0

1

N/A

N/A

N/A

N/A

N/A

N/A

N/A

2

0

1

0

100MHz

50MHz

66MHz

33MHz

HI-Z

14.318MHz

16.67MHz

3

0

1

1

100MHz

50MHz

66MHz

33MHz

48MHz

14.318MHz

16.67MHz

4, 7, 8

1

0

0

TCLK/2

TCLK/4

TCLK/4

TCLK/8

TCLK/2

TCLK

TCLK/16

5, 6

1

0

1

N/A

N/A

N/A

N/A

N/A

N/A

N/A

2

1

1

0

133MHz

66MHz

66MHz

33MHz

HI-Z

14.318MHz

16.67MHz

3

1

1

1

133MHz

66MHz

66MHz

33MHz

48MHz

14.318MHz

16.67MHz

4, 7, 8

NOTES:

1. Required for board level ‘‘bed-of-nails” testing.

2. Used to support Intel confidential application.

3. 48MHz PLL disabled to reduce component jitter. 48MHz outputs to be held Hi-Z instead of driven to LOW state.

4. ‘‘Normal” mode of operation.

5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133MHz CPU select logic.

6. Required for DC output impedance verification.

7. Frequency accuracy of 48MHz must be +167 PPM to match USB default.

8. Range of reference frequency allowed is MIN = 14.316MHz, NOMINAL = 14.31818MHz, MAX = 14.32MHz

CLOCK OUTPUT

TARGET FREQUENCY (MHz)

ACTUAL FREQUENCY (MHz)

PPM

48.0

48.008

167