Philips Semiconductors

Preliminary specification

PCK2010

CK98 (100/133MHz) Spread Spectrum System Clock

Generator

1999 Mar 01

10

APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL

PARAMETER

LIMITS

LIMITS

UNIT

NOTES

SYMBOL

PARAMETER

133MHz MODE

100MHz MODE

UNIT

NOTES

MIN

MAX

MIN

MAX

IOAPIC CLK period

60.0

64.0

60.0

64.0

ns

2, 9

IOAPIC CLK HIGH time

25.5

n/a

25.5

n/a

ns

5, 10

IOAPIC CLK LOW time

25.3

n/a

25.3

n/a

ns

6, 10

IOAPIC CLK rise time

0.4

1.6

0.4

1.6

ns

8

IOAPIC CLK fall time

0.4

1.6

0.4

1.6

ns

8

IOAPIC CLK cycle-cycle jitter

500

500

ps

DUTY CYCLE

IOAPIC CLK Duty Cycle

45

55

45

55

%

1

IOAPIC CLK pin-pin skew

250

250

ps

2

3V66 CLOCK OUTPUT, 3V66 (0–3) (LUMP CAPACITANCE TEST LOAD = 30 pF)

SYMBOL

PARAMETER

LIMITS

LIMITS

UNIT

NOTES

SYMBOL

PARAMETER

133MHz MODE

100MHz MODE

UNIT

NOTES

MIN

MAX

MIN

MAX

3V66 CLK period

15.0

16.0

15.0

16.0

ns

2, 9, 4

3V66 CLK HIGH time

5.25

n/a

5.25

n/a

ns

5, 10

3V66 CLK LOW time

5.05

n/a

5.05

n/a

ns

6, 10

3V66 CLK rise time

0.4

1.6

0.4

1.6

ns

8

3V66 CLK fall time

0.4

1.6

0.4

1.6

ns

8

3V66 CLK cycle-cycle jitter

500

500

ps

DUTY CYCLE

3V66 CLK Duty Cycle

45

55

45

55

%

1

3V66 CLK pin-pin skew

250

250

ps

2

48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

f

Frequency, Actual

Determined by PLL

divider ratio

48.008

MHz

Deviation from 48MHz

(48.008 – 48)/48

+167

ppm

Output rise edge rate

1

4

ns

Output fall edge rate

1

4

ns

Duty Cycle

45

55

%

133MHz

100MHz

CLK cycle-cycle jitter

MIN

MAX

MIN

MAX

ps

500

500

Frequency stabilization from Power-up (cold start)

3

ms

NOTES:

1. See Figure 3 for measure points.