2000 Nov 22

9

Philips Semiconductors

Product specification

65

× 102 pixels matrix LCD driver

PCF8812

9

ADDRESSING

Data is downloaded in bytes into the RAM matrix of the PCF8812 as indicated in Figs.3, 4, 5 and 6. The display RAM

has a matrix of 65

× 102 bits. The columns are addressed by the address pointer. The address ranges are: X0 to X101

(1100101) and Y0 to Y8 (1000). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1)

the Y address increments after each byte (see Fig.6). After the last Y address (Y = 8) Y wraps around to 0 and X

increments to address the next column. In horizontal addressing mode (V = 0) the X address increments after each byte

(see Fig.5). After the last X address (X = 101) X wraps around to 0 and Y increments to address the next row. After the

very last address (X = 101 and Y = 8) the address pointers wrap around to address (X = 0 and Y = 0).

9.1

Data structure

handbook, full pagewidth

MGT638

0

8

0

101

X address

Y address

MSB

LSB

MSB

LSB

Fig.4 RAM format addressing.

handbook, full pagewidth

MGS397

09

110

2

3

4

5

6

7

8

0

8

917

0

101

X address

Y address

Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).