PCF8812USLASH2 datasheet(6/36 Pages) PHILIPS

6 / 36 page

2000 Nov 22

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8812

7.1.8

T1 TO T5: TEST PADS

T1, T3, T4 and T5 must be connected to VSS, T2 must be

left open-circuit. Not accessible to user.

7.1.9

SDIN: SERIAL DATA LINE

Serial data input line.

7.1.10

SCLK: SERIAL CLOCK LINE

Input for the clock signal 0 to 4.0 Mbits/s.

7.1.11

D/C: MODE SELECT

Input to select either command/address or data input.

7.1.12

SCE: CHIP ENABLE

The enable pin allows data to be clocked in; the signal is

active LOW.

7.1.13

OSC: OSCILLATOR

When the on-chip oscillator is used this input must be

connected to VDD. An external clock signal, if used, is

connected to this input. If the oscillator and external clock

are both inhibited by connecting the OSC pin to VSS the

display is not clocked and may be left in a DC state.

To avoid this the chip should always be put into

Power-down mode before stopping the clock.

7.1.14

RES: RESET

This signal will reset the device and must be applied to

properly initialize the chip; the signal is active LOW.

FUNCTIONAL DESCRIPTION

8.1

Oscillator

The on-chip oscillator provides the clock signal for the

display system. No external components are required and

the OSC input must be connected to VDD. An external

clock signal, if used, is connected to this input.

8.2

Address Counter (AC)

The address counter assigns addresses to the display

data RAM for writing. The X address X6 to X0 and the

Y address Y3 to Y0 are set separately. After a write

operation the address counter is automatically

incremented by 1 according to the V flag (see Chapter 9).

8.3

Display Data RAM (DDRAM)

The PCF8812 contains a 65

× 102 bit static RAM which

stores the display data. The RAM is divided into 8 banks of

102 bytes (8

× 8 × 102 bits) and one bank of 102 bits

× 102 bits). During RAM access, data is transferred to

the RAM via the serial interface. There is a direct

correspondence between the X address and the column

output number.

8.4

Timing generator

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not affected by operations on the data buses.

8.5

Display address counter

The display is generated by continuously shifting rows of

RAM data to the dot matrix LCD via the column outputs.

The display status (all dots on/off and normal/inverse

video) is set by bits E and D in the command ‘display

control’ (see Table 2).

8.6

LCD row and column drivers

The PCF8812 contains 65 row and 102 column drivers,

which connect the appropriate LCD bias voltages in

sequence to the display in accordance with the data to be

displayed. Figure 2 shows typical waveforms. Unused

outputs should be left unconnected.

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