1999 Aug 16

30

Philips Semiconductors

Product specification

65

× 102 pixels matrix LCD driver

PCF8548

Fig.21 External high voltage generation is used.

The number of I/Os depends on the application.

handbook, full pagewidth

MGS420

≥3

DISPLAY 102

× 65

VDD

I/O

VSS

VLCD

CVDD

PCF8548

102

32

33

The pinning of the PCF8548 is optimized for single plane wiring e.g. for chip-on-glass display modules, or for TCP.

Display size: 65

× 102 pixels. The required minimum value for the external capacitors in an application with the PCF8548

To reduce the sensitivity of the reset to ESD/EMC disturbances for a COG application, it is strongly recommended to

implement on the glass (ITO) a series input resistance in the reset line (The recommended minimum value is 8 k

Ω).

19 CHIP INFORMATION

20 PAD INFORMATION

PAD

VALUE

UNIT

Minimum bump pitch

70

µm

Pad size, alumin

62

× 100

µm

Bumps

50 (

±6) × 90 (±6) × 17.5 (±5)

µm

Wafer thickness without bumps

U/2 = 381; U/9 = 525

µm