PCF8548 datasheet(6/40 Pages) PHILIPS

6 / 40 page

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8548

BLOCK DIAGRAM FUNCTIONS

8.1

Oscillator

The on-chip oscillator provides the clock signal for the

display system. No external components are required and

the OSC input must be connected to VDD1. An external

clock signal (if used), is connected to this input.

8.2

I2C-bus interface

The I2C-bus interface receives and executes the

commands sent via the I2C-bus. It also receives RAM data

and sends it to the RAM.

8.3

Display control logic

The display control logic generates the control signals to

read from the RAM via the 102 bits parallel port. It also

generates the control signals for the row and column

drivers.

8.4

Display Data RAM (DDRAM)

The PCF8548 contains a 65

× 102 bit static RAM which

stores the display data. The RAM is divided into 8 banks of

102 bytes and 1 bank of 102 bits [(8

× 8+1) × 102 bits].

During RAM access, data is transferred to the RAM via the

I2C-bus interface. There is a direct correspondence

between the X address and column output number.

8.5

Timing generator

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not disturbed by operations on the I2C-bus.

8.6

LCD row and column drivers

The PCF8548 contains 65 row and 102 column drivers,

which connect the appropriate LCD bias voltages to the

display in accordance with the data to be displayed.

Figure 2 shows typical waveforms. Unused outputs should

be left unconnected.

INITIALIZATION

Immediately following Power-on, all internal registers and

the RAM content are undefined. A reset pulse must first be

applied.

Reset is accomplished by applying an external RES pulse

(active LOW). When reset occurs within the specified time

all internal registers are initialized, however the RAM is still

undefined. The state after reset is described in

Section 12.1.

The RES input must be

≤0.3 VDD when VDD reaches

VDD(min) (or higher) within a maximum time tVHRL after VDD

goes HIGH (see Fig.17).

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