PCF8548 datasheet(15/40 Pages) PHILIPS

15 / 40 page

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8548

11.2

I2C-bus protocol

The PCF8548 supports command, data write and status

read access.

Before any data is transmitted on the I2C-bus, the device

which should respond is addressed first. Two 7-bit slave

addresses (0111100 and 0111101) are reserved for the

PCF8548. The least significant bit of the slave address is

set by connecting the input SA0 to either logic 0 (VSS1)or

logic 1 (VDD1).

The I2C-bus protocol is illustrated in Fig.14.

The sequence is initiated with a START condition (S) from

the I2C-bus master which is followed by the slave address.

All slaves with the corresponding address acknowledge in

parallel, all the others will ignore the I2C-bus transfer. After

acknowledgement, one or more command words follow

which define the status of the addressed slaves.

A command word consists of a control byte, which defines

Co and D/C, plus a data byte (see Fig.14 and Table 1).

The last control byte is tagged with a cleared most

significant bit (i.e. the continuation bit Co). After a control

byte with a cleared Co bit, only data bytes will follow. The

state of the D/C bit defines whether the data byte is

interpreted as a command or as RAM data.

The control and data bytes are also acknowledged by all

addressed slaves on the bus.

After the last control byte, depending on the D/C bit setting,

either a series of display data bytes or command data

bytes may follow. If the D/C bit is set to logic 1, these

display bytes are stored in the display RAM at the address

specified by the data pointer. The data pointer is

automatically updated and the data is directed to the

intended PCF8548 device. If the D/C bit of the last control

byte is set to logic 0, these command bytes will be

decoded and the setting of the device will be changed

according to the received commands. The

acknowledgement after each byte is made only by the

addressed slave. At the end of the transmission the

I2C-bus master issues a STOP condition (P).

If the R/W bit is set to logic 1 the chip will output data

immediately after the slave address if the D/C bit, which

was sent during the last write access, is set to logic 0. If no

acknowledge is generated by the master after a byte, the

driver stops transferring data to the master.

Fig.14 I2C-bus protocol.

handbook, full pagewidth

MGS401

S 011110

acknowledgement

from PCF8548

acknowledgement

from PCF8548

acknowledgement

from PCF8548

acknowledgement

from PCF8548

acknowledgement

from PCF8548

control byte

data byte

≥ 0 bytes

1 byte

slave address

Write mode

command word

MSB . . . . . . . . . . . LSB

≥ 0 bytes

A P

control byte

S 011110

acknowledgement

from PCF8548

acknowledgement

from master

PCF8548

slave address

status bytes

slave address

Read mode

00000 0

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