ST10F276 datasheet(206/229 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F276

206/229

23.8.18

Multiplexed bus

VDD = 5V ±10%, VSS = 0V, TA = –40 to +125°C, CL = 50pF,

ALE cycle time = 6 TCL + 2tA + tC + tF (75ns at 40 MHz CPU clock without wait states).

Table 104.

Multiplexed bus

Symbol

Parameter

FCPU = 40 MHz

TCL = 12.5ns

Variable CPU clock

1/2 TCL = 1 to 64 MHz

Min.

Max.

Min.

Max.

CC ALE high time

4 + tA

–

TCL – 8.5 + tA

–

CC Address setup to ALE

1.5 + tA

TCL – 11 + tA

CC Address hold after ALE

4 + tA

TCL – 8.5 + tA

ALE falling edge to RD,

WR (with RW-delay)

4 + tA

TCL – 8.5 + tA

ALE falling edge to RD,

(no RW-delay)

– 8.5 + tA

t10

Address float after RD,

WR (with RW-delay)(1)

–

t11

Address float after RD,

(no RW-delay)1

18.5

TCL + 6

t12

RD, WR low time

(with RW-delay)

15.5 + tC

–

2TCL – 9.5 + tC

–

t13

RD, WR low time

(no RW-delay)

28 + tC

3TCL – 9.5 + tC

t14

RD to valid data in

(with RW-delay)

–

6 + tC

–

2TCL – 19 + tC

t15

RD to valid data in

(no RW-delay)

18.5 + tC

3TCL – 19 + tC

t16

SR ALE low to valid data in

17.5 +

+ tA + tC

3TCL – 20 +

+ tA + tC

t17

Address/Unlatched CS

to valid data in

20 + 2tA +

+ tC

4TCL – 30 +

+ 2tA + tC

t18

Data hold after RD

rising edge

0–

–

t19

SR Data float after RD1

–

16.5 + tF

–

2TCL – 8.5 + tF

t22

CC Data valid to WR

10 + tC

–

2TCL – 15 + tC

–

t23

CC Data hold after WR

4 + tF

2TCL – 8.5 + tF

t25

ALE rising edge after

RD, WR

15 + tF

2TCL – 10 + tF

t27

Address/Unlatched CS

hold after RD, WR

10 + tF

2TCL – 15 + tF

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