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PCD5002 датащи(PDF) 23 Page - NXP Semiconductors |
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PCD5002 датащи(HTML) 23 Page - NXP Semiconductors |
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23 / 48 page ![]() 1997 Jun 24 23 Philips Semiconductors Product specification Advanced POCSAG and APOC-1 Paging Decoder PCD5002 Table 21 Alert set-up register (04H; write) Note 1. Bits D7 and D6 correspond to function bits 20 and 21 respectively in the address codeword, which designate the POCSAG call type as shown in Table 1. BIT (MSB D7) VALUE DESCRIPTION D0 0 call alert via cadence register 1 POCSAG call alert (pattern selected by D7 and D6) D1 0 LOW level acoustic alert (ATL), pulsed vibrator alert (25 Hz) 1 HIGH level acoustic alert (ATL + ATH), continuous vibrator alert D2 0 normal alerts (acoustic and LED) 1 warbled alerts: 16 Hz (LED: on/off, ATL/ATH: alternate fAWH, fAWL) D3 1 acoustic alerts enable (ATL, ATH) D4 1 vibrator alert enabled (VIB) D5 1 LED alert enabled (LED) D7 and D6(1) 0 0 POCSAG alert pattern FC = 00, see Fig.9 (a) 0 1 POCSAG alert pattern FC = 01, see Fig.9 (b) 1 0 POCSAG alert pattern FC = 10, see Fig.9 (c) 1 1 POCSAG alert pattern FC = 11, see Fig.9 (d) Fig.9 POCSAG alert patterns. handbook, full pagewidth MLC251 (a) (b) (c) (d) 0 0 D7, D6 0 1 1 0 1 1 |
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