PCD5002 datasheet(22/48 Pages) PHILIPS

22 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

8.30

Real time clock

The PCD5002 provides a periodic reference pulse at

output REF. The frequency of this signal can be selected

by SPF programming:

• 32768 Hz

• 50 Hz (square-wave)

• 2Hz

• 1⁄60 Hz.

The 32768 Hz signal does not have a fixed period, it

consists of 32 pulses distributed over 75 main oscillator

cycles at 76.8 kHz. The timing is illustrated in Fig.15.

When programmed for 1

⁄60 Hz (1 pulse per minute) the

pulse at output REF is held off while the receiver is

enabled.

Except for the 50 Hz frequency the pulse width tRFP is

equal to one decoder clock period.

The real time clock counter runs continuously irrespective

of the operating condition of the PCD5002. It contains a

seconds register (maximum 59) and a 1

⁄100 second

to via the I2C-bus. The bit allocation of both registers is

shown in Tables 19 and 20.

Table 19 Real time clock; seconds register (01H;

read/write)

BIT

(MSB D7)

VALUE

DESCRIPTION

−

16 s

−

32 s

not used: ignored when written,

undetermined when read

not used: ignored when written,

undetermined when read

Table 20 Real time clock; 1

⁄100 second register (02H;

read/write)

8.31

Periodic interrupt

A periodic interrupt can be realised with the periodic

interrupt counter. This 8-bit counter is incremented every

⁄100 s and produces an interrupt when it reaches the value

stored in the periodic interrupt modulus register.

The counter register is then reset and counting continues.

Operation is started by writing a non-zero value to the

modulus register. Writing a zero will stop interrupt

generation immediately and will halt the periodic interrupt

counter after 2.55 s.

The modulus register is write-only, the counter register is

read only. Both registers have the same index address

(05H).

8.32

Received call delay

Call reception (detection of an enabled RIC) causes both

the periodic interrupt modulus and the counter register to

be reset.

Since the periodic interrupt counter runs for another 2.55 s

after a reset, the received call delay (in 1

⁄100 s units) can be

determined by reading the counter register.

BIT

(MSB D7)

VALUE

DESCRIPTION

−

0 01 s

−

0.02 s

−

0.04 s

−

0.08 s

−

0.16 s

−

0.32 s

−

0.64 s

not used: ignored when written,

undetermined when read

PCD5002 датащи(PDF) 22 Page - NXP Semiconductors

PCD5002 датащи(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL