PCD5002 datasheet(6/48 Pages) PHILIPS

6 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

FUNCTIONAL DESCRIPTION

8.1

Introduction

The PCD5002 is a very low power decoder and pager

controller specifically designed for use in new generation

radio pagers. The architecture of the PCD5002 allows for

flexible application in a wide variety of radio pager designs.

The PCD5002 is fully compatible with

“CCIR Radio paging

Code No. 1” (also known as the POCSAG code) operating

at data rates of 512, 1200 and 2400 bits/s using a single

oscillator crystal of 76.8 kHz.

The PCD5002 also supports the new Advanced Pager

Operator’s Code Phase 1 (APOC-1). This compatible

extension to the POCSAG code improves battery

economy by introducing ‘cycles’ and batch numbering.

A cycle consists of 5 or 15 standard POCSAG batches.

Each pager will be allocated a batch number in addition to

its POCSAG address and it will only search for its address

during this batch.

In addition to the standard POCSAG sync word (used also

in APOC-1) the PCD5002 is also capable of recognizing

up to 4 User Programmable Sync Words (UPSWs).

This permits the reception of both private services and

POCSAG or APOC-1 transmissions via the same radio

channel. As an option reception of a UPSW may activate

Continuous Data Decoding (CDD).

Used together with the Philips UAA2080 or UAA2082

paging receiver, the PCD5002 offers a highly

sophisticated, miniature solution for the radio paging

market. Control of an RF synthesizer circuit is also

provided to ease alignment and channel selection.

On-chip EEPROM provides storage for user addresses

(Receiver Identity Codes or RICs) and Special

Programmed Functions (SPFs) and UPSWs, which

eliminates the need for external storage devices and

interconnection. For other non-volatile storage 20 bytes of

general purpose EEPROM are available. The low

EEPROM programming voltage makes the PCD5002 well

suited for ‘over-the-air’ programming/reprogramming.

On request from an external controlling device or

automatically (by SPF programming), the PCD5002 will

provide standard POCSAG alert cadences by driving a

standard acoustic ‘beeper’. Non-standard alert cadences

may be generated via a cadence register or a dedicated

control input.

The PCD5002 can also produce a HIGH level acoustic

alert as well as drive an LED indicator and a vibrator motor

via external bipolar transistors.

The PCD5002 contains a low-power, high-efficiency

voltage converter (doubler) designed to provide a higher

voltage supply to LCD drivers or microcontrollers.

In addition, an independent level shifted interface is

provided allowing communication to a microcontroller

operating at a higher voltage than the PCD5002.

Interface to such an external device is provided by an

I2C-bus which allows received call identity and message

data, data for the programming of the internal EEPROM,

alert control and pager status information to be transferred

between the devices. Pager status includes features

provided by the PCD5002 such as battery-low and

out-of-range indications. A dedicated interrupt line

minimizes the required microcontroller activity.

A selectable low frequency timing reference is provided for

use in real time clock functions.

Data synchronization is achieved by the Philips patented

ACCESS® algorithm ensuring that maximum advantage is

made of the POCSAG code structure particularly in fading

radio signal conditions. The algorithm allows for data

synchronization without preamble detection whilst

minimizing battery power consumption. The APOC-1 code

uses an extended version of the ACCESS®

synchronization algorithm.

Random (and optional) burst error correction techniques

are applied to the received data to optimize the call

success rate without increasing the falsing rate beyond

specified POCSAG levels.

8.2

The POCSAG paging code

A transmission using the

“CCIR Radio paging Code No. 1”

(POCSAG code) is constructed in accordance with the

following rules (see Fig.3).

The transmission is started by sending a preamble,

consisting of at least 576 continuously alternating bits

(10101010...). The preamble is followed by an arbitrary

number of batch blocks. Only complete batches are

transmitted.

Each batch comprises 17 codewords of 32 bits each.

The first codeword is a synchronization codeword with a

fixed pattern. The sync word is followed by 8 frames

(0 to 7) of 2 codewords each, containing message

information. A codeword in a frame can either be an

address, message or idle codeword.

Idle codewords also have a fixed pattern and are used to

fill empty frames or to separate messages.

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