ISL6721 datasheet(16/21 Pages) INTERSIL

16 / 21 page

FN9110.4

April 13, 2007

A block diagram of the feedback control loop follows in

Figure 7.

The loop compensation is placed around the Error Amplifier

(EA) on the secondary side of the converter. The primary

side amplifier located in the control IC is used as a unity gain

inverting amplifier and provides no loop compensation. A

Type 2 error amplifier configuration was selected as a

precaution in case operation in continuous mode should

occur at some operating point.

Development of a small signal model for current mode

control is rather complex. The method of reference [1] was

selected for its ability to accurately predict loop behavior. To

further simplify the analysis, the converter will be modeled as

a single output supply with all of the output capacitance

reflected to the 3.3V output. Once the “single” output system

is compensated, adjustments to the compensation will be

required based on actual loop measurements.

The first parameter to determine is the peak current

feedback loop gain. Since this application is low power, a

resistor in series with the source of the power switching

MOSFET is used for the current feedback signal. For higher

power applications, a resistor would dissipate too much

power and current transformer would be used instead.

There is limited flexibility to adjust the current loop behavior

due to the need to provide overcurrent protection. Current

limit and the current loop gain are determined by the current

sense resistor and the ISET threshold. ISET was set at 1.0V,

near its maximum, to minimize noise effects. When

determining ISET, the internal gain and offset of the ISENSE

signal in the control IC must be taken into account. The

maximum peak primary current was determined earlier to be

1.87A, so a choice of 2.25A peak primary current for current

limit is reasonable. A current gain, AEXT, of 0.5 V/A was

selected to achieve this.

The control to output transfer function may be represented

as [2]

if we ignore the current feedback sampled-data effects.

The value of K may be determined by assuming all of the

output power is delivered by the 3.3V output at the threshold

of current limit. The maximum power allowed was

determined earlier as 15W, so

where AEXT is the external gain of the current feedback

network, ACS is the IC internal gain, and ACOMP is the gain

between the error amplifier and the PWM comparator.

The Type 2 compensation configuration has two poles and

one zero. The first pole is at the origin, and provides the

integration characteristic which results in excellent DC

regulation. Referring to the “Typical Application - 48V Input

Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A” on page 3,

FIGURE 7. FEEDBACK CONTROL LOOP

PWM

POWER

STAGE

REF

ISOLATION

ERROR AMPLIFIER

PRIMARY SIDE AMPLIFIER

VOUT

FIGURE 8. TYPE 2 ERROR AMPLIFIER

REF

VOUT

VERROR

ISET

2.25

0.8

0.5

0.100

•

1.00

(EQ. 26)

------

•

-----------------------------------

------

-------

-----------------

•

(EQ. 27)

spk max

()

cmax

()

--------------------------

(EQ. 28)

LoadResis

tan

(EQ. 29)

SecondaryInduc

tan

(EQ. 30)

•

--------------------

π R

•

-----------------------------

(EQ. 31)

•

--------------------

•

--------------------------------------

(EQ. 32)

OutputCapaci

tan

(EQ. 33)

OutputCapaci

ceE

tan

(EQ. 34)

cmax

()

ControlVoltageRange

(EQ. 35)

spk max

()

out

------------

Tsw

•

---------------------------------------

3.3

--------

–

×10

•

2.33

–

×10

------------------------------------------

19.5

(EQ. 36)

cmax

()

ISENSE

EXT

•

COMP

---------------------

•

2.93

(EQ. 37)

ISL6721

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