| поискавой системы для электроныых деталей |
|
ISL6721 датащи(PDF) 15 Page - Intersil Corporation |
|
|
|||||||||||||||||||||||||||||
ISL6721 датащи(HTML) 15 Page - Intersil Corporation |
|
15 / 21 page ![]() 15 FN9110.4 April 13, 2007 The final component of MOSFET loss is caused by the charging of the gate capacitance through the device gate resistance. Depending on the relative value of any external resistance in the gate drive circuit, a portion of this power will be dissipated externally. Once the losses are known, the device package must be selected and the heatsinking method designed. Since the design requires a small surface mount part, a SOIC-8 package was selected. A Fairchild FDS2570 MOSFET was selected based on these criteria. The overall losses are estimated at 400mW. Output Filter Design In a flyback design, the primary concern for the design of the output filter is the capacitor ripple current stress and the ripple and noise specification of the output. The current flowing in and out of the output capacitors is the difference between the winding current and the output current. The peak secondary current, ISPK, is 10.73A for the 3.3V output and 4.29A for the 1.8V output. The current flowing into the output filter capacitor is the difference between the winding current and the output current. Looking at the 3.3V output, the peak winding current is ISPK = 10.73A. The capacitor must store this amount minus the output current of 2.5A, or 8.23A. The RMS ripple current in the 3.3V output capacitor is about 3.5A RMS. The RMS ripple current in the 1.8V output capacitor is about 1.4A RMS Voltage deviation on the output during the switching cycle (ripple and noise) is caused by the change in charge of the output capacitance, the equivalent series resistance (ESR), and equivalent series inductance (ESL). Each of these components must be assigned a portion of the total ripple and noise specification. How much to allow for each contributor is dependent on the capacitor technology used. For purposes of this discussion we will assume the following: 3.3V output: 100mV total output ripple and noise ESR: 60mV Capacitor ΔQ: 10mV ESL: 30mV 1.8V output: 50mV total output ripple and noise ESR: 30mV Capacitor ΔQ: 5mV ESL: 15mV For the 3.3V output: The change in voltage due to the change in charge of the output capacitor, ΔQ, determines how much capacitance is required on the output. ESL adds to the ripple and noise voltage in proportion to the rate of change of current into the capacitor (V = L • di/dt). Capacitors having high capacitance usually do not have sufficiently low ESL. High frequency capacitors such as surface mount ceramic or film are connected in parallel with the high capacitance capacitors to address the effects of ESL. A combination of high frequency and high ripple capability capacitors is used to achieve the desired overall performance. The analysis of the 1.8V output is similar to that of the 3.3V output and is omitted for brevity. Two OSCON 4SEP560M (560 μF) electrolytic capacitors and a 22 μF X5R ceramic 1210 capacitor were selected for both the 3.3 and 1.8V outputs. The 4SEP560M electrolytic capacitors are each rated at 4520mA ripple current and 13m Ω of ESR. The ripple current rating of just one of these capacitors is adequate, but two are needed to meet the minimum ESR and capacitance values. The bias output is of such low power and current that it places negligible stress on its filter capacitor. A single 0.1 μF ceramic capacitor was selected. Control Loop Design The major components of the feedback control loop are a programmable shunt regulator, an opto-coupler, and the inverting amplifier of the ISL6721. The opto-coupler is used to transfer the error signal across the isolation barrier. The opto-coupler offers a convenient means to cross the isolation barrier, but it adds complexity to the feedback control loop. It adds a pole at about 10kHz and a significant amount of gain variation due the current transfer ratio (CTR). The CTR of the opto-coupler varies with initial tolerance, temperature, forward current, and age. Pgate QgVgFsw • • = W (EQ. 22) ESR ΔV I SPK I OUT – --------------------------------- ≤ 0.060 10.73 2.5 – ----------------------------- 7.3m Ω == (EQ. 23) C Ispk Iout – () Tr • 2 ΔV • ---------------------------------------------- ≥ 10.73 2.5 – () 2.33 6 – ×10 • 20.010 • ------------------------------------------------------------------- 960 μF == (EQ. 24) L Vdt • di --------------- ≤ 0.030 200 9 – ×10 • 10.73 ---------------------------------------------- 0.56nH == (EQ. 25) ISL6721 |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |