ISL6721 datasheet(14/21 Pages) INTERSIL

14 / 21 page

FN9110.4

April 13, 2007

The RMS current for the primary winding is 0.72A, for the

3.3V output, 4.23A, for the 1.8V output, 1.69A, and for the

bias winding, 85mA.

To minimize the transformer leakage inductance, the primary

was split into two sections connected in parallel and

positioned such that the other windings were sandwiched

between them. The output windings were configured so that

the 1.8V winding is a tap off of the 3.3V winding. Tapping the

1.8V output requires that the shared portion of the

secondary conduct the combined current of both outputs.

The secondary wire gauge must be selected accordingly.

The determination of current carrying capacity of wire is a

compromise between performance, size, and cost. It is

affected by many design constraints such as operating

frequency (harmonic content of the waveform) and the

winding proximity/geometry. It generally ranges between 250

and 1000 circular mils per ampere. A circular mil is defined

as the area of a circle 0.001” (1 mil) in diameter. As the

frequency of operation increases, the AC resistance of the

wire increases due to skin and proximity effects. Using

heavier gauge wire may not alleviate the problem. Instead

multiple strands of wire in parallel must be used. In some

cases Litz wire is required.

The winding configuration selected is:

Primary #1: 40T, 2 #30 bifilar

Secondary: 5T, 0.003” (3 mil) copper foil tapped at 3T

Bias: 17T #32

Primary #2: 40T, 2 #30 bifilar

The internal spacing and insulation system was designed for

1500VDC dielectric withstand rating between the primary

and secondary windings.

Power MOSFET Selection

Selection of the main switching MOSFET requires

consideration of the voltage and current stresses that will be

encountered in the application, the power dissipated by the

device, its size, and its cost.

The input voltage range of the converter is 36VDC to

75VDC. This suggests a MOSFET with a voltage rating of

150V is required due to the flyback voltage likely to be seen

on the primary of the isolation transformer.

The losses associated with MOSFET operation may be

divided into three categories: conduction, switching, and

gate drive.

The conduction losses are due to the MOSFET’s ON

resistance.

where rDS(ON) is the ON resistance of the MOSFET and

Iprms is the RMS primary current. Determining the

conduction losses is complicated by the variation of rDSON

with temperature. As junction temperature increases, so

does rDS(ON), which increases losses and raises the

junction temperature more, and so on. It is possible for the

device to enter a thermal runaway situation without proper

heatsinking. As a general rule of thumb, doubling the 25°C

rDSON specification yields a reasonable value for estimating

the conduction losses at +125°C junction temperature.

The switching losses have two components, capacitive

switching losses and voltage/current overlap losses. The

capacitive losses occur during turn on of the device and may

be calculated as follows:

where Cfet is the equivalent output capacitance of the

MOSFET. Device output capacitance is specified on

datasheets as Coss and is non-linear with applied voltage.

To find the equivalent discrete capacitance, Cfet, a charge

model is used. Using a known current source, the time

required to charge the MOSFET drain to the desired

operating voltage is determined and the equivalent

capacitance may be calculated.

The other component of the switching loss is due to the

overlap of voltage and current during the switching

transition. A switching transition occurs when the MOSFET

is in the process of either turning on or off. Since the load is

inductive, there is no overlap of voltage and current during

the turn on transition, so only the turn off transition is of

significance. The power dissipation may be estimated as:

where tOL is the duration of the overlap period and x ranges

from about 3 through 6 in typical applications and depends

on where the waveforms intersect. This estimate may predict

higher dissipation than is realized because a portion of the

turn off drain current is attributable to the charging of the

device output capacitance (Coss) and is not dissipative

during this portion of the switching cycle.

Pcond

DS ON

() Iprms

•

(EQ. 18)

Pswcap

---

Cfet

Vin

Fsw

•

(EQ. 19)

Cfet

Ichg

•

--------------------

(EQ. 20)

---

PPK

•

≈

(EQ. 21)

D- S

Ippk

To l

FIGURE 6. SWITCHING CYCLE

ISL6721

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