ISL6721 datasheet(10/21 Pages) INTERSIL

10 / 21 page

FN9110.4

April 13, 2007

VCC to LGND with a ceramic capacitor as close to the VCC

and LGND pins as possible.

The total supply current (IC plus ICC) will be higher,

depending on the load applied to GATE. Total current is the

sum of the quiescent current and the average gate current.

Knowing the operating frequency, Fsw, and the MOSFET

gate charge, Qg, the average GATE output current can be

calculated from:

VREF - The 5.00V reference voltage output. Bypass to

LGND with a 0.01

μF or larger capacitor to filter this output as

needed. Using capacitance less than this value may result in

unstable operation.

SS - Connect the soft-start capacitor between this pin and

LGND to control the duration of soft-start. The value of the

capacitor determines both the rate of increase of the duty

cycle during start up, and also controls the overcurrent

shutdown delay.

ISET - A DC voltage between 0.35 and 1.2V applied to this

input sets the pulse-by-pulse overcurrent threshold. When

overcurrent inception occurs, the SS capacitor begins to

discharge and starts the overcurrent delayed shutdown

cycle.

Functional Description

Features

The ISL6721 current mode PWMs make an ideal choice for

low-cost flyback and forward topology applications requiring

enhanced control and supervisory capability. With adjustable

overvoltage and undervoltage thresholds, overcurrent

threshold, and hic-cup delay, a highly flexible design with

minimal external components is possible. Other features

include peak current mode control, adjustable soft-start,

slope compensation, adjustable oscillator frequency, and a

bi-directional synchronization clock input.

Oscillator

The ISL6721 have a sawtooth oscillator with a

programmable frequency range to 1MHz, which can be

programmed with a resistor and capacitor on the RTCT pin.

(Please refer to

Figure 4 for the resistance and capacitance

required for a given frequency.)

Implementing Synchronization

The oscillator can be synchronized to an external clock

applied at the SYNC pin or by connecting the SYNC pins of

multiple ICs together. If an external master clock signal is

used, it must be at least 65% of the free running frequency of

the oscillator for proper synchronization. The external

master clock signal should have a pulse width greater than

20ns. If no master clock is used, the first device to assert

SYNC assumes control of the SYNC signal. An external

SYNC pulse is ignored if it occurs during the first 1/3 of the

switching cycle.

During normal operation the RTCT voltage charges from 1.5

to 3.0V and back during each cycle. Clock and SYNC

signals are generated when the 3.0V threshold is reached. If

an external clock signal is detected during the latter 2/3 of

the charging cycle, the oscillator switches to external

synchronization mode and relies upon the external SYNC

signal to terminate the oscillator cycle. The generation of a

SYNC signal is inhibited in this mode. If the RTCT voltage

exceeds 4.0V (i.e. no external SYNC signal terminates the

cycle), the oscillator reverts to the internal clock mode and a

SYNC signal is generated.

Soft-Start Operation

The ISL6721 features soft-start using an external capacitor

in conjunction with an internal current source. Soft-start is

used to reduce voltage stresses and surge currents during

start up.

Upon start up, the soft-start circuitry clamps the error

amplifier output (COMP pin) to a value proportional to the

soft-start voltage. The error amplifier output rises as the soft-

start capacitor voltage rises. This has the effect of increasing

the output pulse width from zero to the steady state

operating duty cycle during the soft-start period. When the

soft-start voltage exceeds the error amplifier voltage, soft-

start is completed. Soft-start forces a controlled output

voltage rise. Soft-start occurs during start-up and after

recovery from a fault condition or overcurrent shutdown. The

soft-start voltage is clamped to 4.5V.

Gate Drive

The ISL6721 is capable of sourcing and sinking 1A peak

current. Separate collector supply (VC) and power ground

(PGnd) pins help isolate the IC’s analog circuitry from the

high power gate drive noise. To limit the peak current

through the IC, an external resistor may be placed between

the totem-pole output of the IC (GATE pin) and the gate of

the MOSFET. This small series resistor also damps any

oscillations caused by the resonant tank of the parasitic

inductances in the traces of the board and the FET’s input

capacitance.

Slope Compensation

For applications where the maximum duty cycle is less than

50%, slope compensation may be used to improve noise

immunity, particularly at lighter loads. The amount of slope

compensation required for noise immunity is determined

empirically, but is generally about 10% of the full scale

current feedback signal. For applications where the duty

cycle is greater than 50%, slope compensation is required to

prevent instability. Slope compensation is a technique in

which the current feedback signal is modified by adding

additional slope to it. The minimum amount of slope

compensation required corresponds to 1/2 the inductor

downslope. However, adding excessive slope compensation

(EQ. 5)

Igate

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ISL6721

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