ISL51002 datasheet(22/32 Pages) INTERSIL

22 / 32 page

December 22, 2006

Technical Highlights

The ISL51002 provides all the features of traditional triple

channel video AFEs, but adds several next-generation

enhancements, bringing performance and ease of use to

new levels.

DPLL

All video AFEs must phase lock to an HSYNC signal,

supplied either directly or embedded in the video stream

(Sync On Green). Historically this has been implemented as

a traditional analog PLL. At SXGA and lower resolutions, an

analog PLL solution has proven adequate, if somewhat

troublesome (due to the need to adjust charge pump

currents, VCO ranges and other parameters to find the

optimum trade-off for a wide range of pixel rates).

As display resolutions and refresh rates have increased,

however, the pixel period has shrunk. An XGA pixel at a

60Hz refresh rate has 15.4ns to change and settle to its new

value. But at UXGA 75Hz, the pixel period is 4.9ns. Most

consumer graphics cards (even the ones with “350MHz”

DACs) spend most of that time slewing to the new pixel

value. The pixel may settle to its final value with 1ns or less

before it begins slewing to the next pixel. In many cases it

rings and never settles at all. So precision, low-jitter

sampling is a fundamental requirement at these speeds, and

a difficult one for an analog PLL to meet.

The ISL51002's DPLL has less than 250ps of jitter, peak to

peak, and independent of the pixel rate. The DPLL generates

64 phase steps per pixel (vs. the industry standard 32), for

fine, accurate positioning of the sampling point. The crystal-

locked NCO inside the DPLL completely eliminates drift due to

charge pump leakage, so there is inherently no frequency or

phase change across a line. An intelligent all-digital loop

filter/controller eliminates the need for the user to have to

program or change anything (except for the number of pixels)

to lock over a range from interlaced video (10MHz or higher)

to UXGA 60Hz (165MHz, with the ISL51002-165).

The DPLL eliminates much of the performance limitations and

complexity associated with noise-free digitization of high

speed signals.

Automatic Black Level Compensation (ABLC™)

and Gain Control

Traditional video AFEs have an offset DAC prior to the ADC,

to both correct for offsets on the incoming video signals and

add/subtract an offset for user “brightness control” without

sacrificing the 10-bit dynamic range of the ADC. This

solution is adequate, but it places significant requirements

on the system's firmware, which must execute a loop that

detects the black portion of the signal and then servos the

offset DACs until that offset is nulled (or produces the

desired ADC output code). Once this has been

accomplished, the offset (both the offset in the AFE and the

offset of the video card generating the signal) is subject to

drift - the temperature inside a monitor or projector can

easily change +50°C between power-on/offset calibration on

a cold morning and the temperature reached once the

monitor and the monitor's environment have reached steady

state. Offset can drift significantly over +50°C, reducing

image quality and requiring that the user do a manual

calibration once the monitor has warmed up.

In addition to drift, many AFEs exhibit interaction between

the offset and gain controls. When the gain is changed, the

magnitude of the offset is changed as well. This again

increases the complexity of the firmware as it tries to

optimize gain and offset settings for a given video input

signal. Instead of adjusting just the offset, then the gain, both

have to be adjusted interactively until the desired ADC

output is reached.

The ISL51002 simplifies offset and gain adjustment and

completely eliminates offset drift using its Automatic Black

Level Compensation (ABLC™) function. ABLC™ monitors the

black level and continuously adjusts the ISL51002's 10-bit

offset DACs to null out the offset. Any offset, whether due to

the video source or the ISL51002's analog amplifiers, is

eliminated with 10-bit accuracy. Any drift is compensated for

well before it can have a visible effect. Manual offset

adjustment control is still available (a 10-bit register allows the

firmware to adjust the offset ±64 codes in exactly 1 ADC LSB

increments). Gain is now completely independent of offset

(adjusting the gain no longer affects the offset, so there is no

longer a need to program the firmware to cope with interactive

offset and gain controls).

Finally, there should be no concerns over ABLC™ itself

introducing visible artifacts; it doesn't. ABLC™ functions at a

very low frequency, changing the offset in 1 LSB increments,

so it can't cause visible brightness fluctuations. And once

ABLC™ is locked, if the offset doesn't drift, the DACs won't

change. If desired, ABLC™ can be disabled, allowing the

firmware to work in the traditional way, with 10-bit offset

DACs under the firmware's control.

Gain and Offset Control

To simplify image optimization algorithms, the ISL51002

features fully-independent gain and offset adjustment.

Changing the gain does not affect the DC offset, and the

weight of an Offset DAC LSB does not vary depending on

the gain setting.

The full-scale gain is set in the three sets of registers (0x12

and 0x13-0x16 and 0x17).Each set of gain registers is

divided into an 8-bit MSB register (0x12, 0x14 and 0x16) and

a 2-bit LSB register providing a 10-bit gain value that both

allows for 8-bit control compatible with the 8-bit family of

AFEs and allows for the expansion of the gain resolution in

future AFEs without significant firmware changes. The

ISL51002 can accept input signals with amplitudes ranging

from 0.35VP-P to 1.4VP-P.

ISL51002

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