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ISL51002 датащи(PDF) 20 Page - Intersil Corporation

номер детали ISL51002
подробное описание детали  10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features
PDF  32 Pages
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производитель  INTERSIL [Intersil Corporation]
домашняя страница  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL51002 датащи(HTML) 20 Page - Intersil Corporation

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20
December 22, 2006
0x52
Phase ADJ MASK V, (0x01)
2:0
PADJ Exclude v2
Vertical line mask: How many lines to exclude before the
leading edge of vsync
000: 0 lines
001: 1 lines (default)
010: 2 lines
011: 4 lines
100: 6 lines
101: 8 lines
110: 10 lines
111: 12 lines
3N/A
6:4
PADJ Exclude v1
Choose how many lines to exclude after the leading edge of
vsync (typically used to exclude VBI data)
000: 5 lines (default)
001: 18 lines
010: 19 lines (480i)
011: 20 lines (1080i)
100: 22 lines (576i)
101: 25 lines (720p)
110: 41 lines (480p/1080p)
111: 44 lines (576p)
0x53
Horizontal pixel mask 1,
(0x01)
7:0
PADJ Exclude h1
If a value of ‘N’ is programmed in this register, 2*N pixels after
the active edge of HSOUT will be excluded from data
collection.
Must be >0 for proper operation.
0x54
Horizontal pixel mask 2,
(0x01)
7:0
PADJ Exclude h2
If a value of ‘N’ is programmed in this register, 2*N pixels
before the active edge of HSOUT will be excluded from data
collection.
Must be >0 for proper operation.
0x55
Phase Adjust Command
Options, (0x20)
0
PADJ Blue Disable
Enable/disable blue color for measurement
0: enable
1: disable
1
PADJ Green Disable
Enable/disable green color for measurement
0: enable
1: disable
2
PADJ Red Disable
Enable/disable red color for measurement
0: enable
1: disable
3
PADJ Adjust Search Option Search option for auto phase adjustment
0: best phase
1: worst phase
4
PADJ Adjust Speed
This is a hidden bit for customers. It decides whether the
search steps are 28 (fast) or 64 vsync intervals (slow).
0: 28 VSYNCs
1: 64 VSYNCs
5
Update Phase on VSYNC
0: phase updated immediately
1: phase updated on VSYNC (default)
6
PADJ Soft Reset
0: Normal operation
1: Reset all phase adjust state machines
Take high then low to reset phase adjust block
7
Reserved
Set to 0
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
DESCRIPTION
ISL51002



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