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ISL51002 датащи(PDF) 13 Page - Intersil Corporation |
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ISL51002 датащи(HTML) 13 Page - Intersil Corporation |
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13 / 32 page ![]() 13 December 22, 2006 CONFIGURATION REGISTERS 0x10 Input Configuration, (0x00) 1:0 Input Channel Select Sets video muxes as well as HSYNC, VSYNC, and SOG input muxes. 0: CH0 1: CH1 2: CH2 (single-ended mode only) 3: CH3 (single-ended mode only) 2 Differential Mode Enable 0: Single-Ended Mode 1: Differential Mode 3 DC Coupled Input Enable 0: AC-coupled Inputs 1: DC-coupled Inputs 4 RGB YUV 0: RGB inputs (Clamp DAC = 300mV for R, G, B, half scale analog shift for R, G, and B, base ABLC target code = 0x00 for R, G, and B) 1: YPbPr inputs (Clamp DAC = 600mV for R and B, 300mV for G, half scale analog shift for G channel only, base ABLC target code = 0x00 for G, = 0x80 for R and B) 5 High Voltage Enable 0: Normal Input Range 1: Expanded 2.2V Input Range 6 EXT Clamp SEL 0: Internal CLAMP generation 1: External CLAMP source 7 EXT Clamp POL 0: Active high external CLAMP 1: Active low external CLAMP 0x11 Sync Source Selection, (0x00) 0 Sync Select 0: Automatic (HSYNC, VSYNC sources selected based on sync activity. Multiplexer settings chosen are displayed in the Input Characteristics register.) 1: Manual (bits 1and 2 determine HSYNC and VSYNC source) 1 HSYNC Source 0: HSYNC input pin 1: SOG 2 VSYNC Source 0: VSYNC input pin 1: Sync Separator output 0x12 Red Gain MSB,(0x55) 7:0 Red Gain MSB Red channel gain, where: gain (V/V) = 0.5 + [9:0]/682 MSB/LSB 0x00 00: gain = 0.5 V/V (1.4VP-P input = full range of ADC) 0x55 00: gain = 1.0 V/V (0.7VP-P input = full range of ADC) 0xFF C0: gain = 2.0 V/V (0.35VP-P input = full range of ADC) 0x13 Red Gain LSB,(0x00) 5:0 N/A 7:6 Red Gain LSB 2 LSBs of 10-bit gain word 0x14 Green Gain MSB,(0x55) 7:0 Green Gain MSB See Red Gain 0x15 Green Gain LSB,(0x00) 5:0 N/A 7:6 Green Gain LSB See Red Gain 0x16 Blue Gain MSB,(0x55) 7:0 Blue Gain MSB See Red Gain 0x17 Blue Gain LSB,(0x00) 5:0 N/A 7:6 Blue Gain LSB See Red Gain 0x18 Red Offset MSB,(0x80) 7:0 Red Offset MSB ABLC off: upper 8 bits to Red offset DAC ABLC enabled: Red digital offset 0x00 00 = min DAC value or -0x80 digital offset 0x80 00 = mid DAC value or 0x00 digital offset, 0xFF C0= max DAC value or +0x7F digital offset Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BITS FUNCTION NAME DESCRIPTION ISL51002 |
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