M700000002 datasheet(82/128 Pages) SPANSION

82 / 128 page

Am70PDL127BDH/Am70PDL129BDH

November 25, 2003

AD VAN C E

INFORM ATION

GENERAL DESCRIPTION (LV640M)

The Am29LV640MH is a 64 Mbit, 3.0 volt single power

supply flash memory device organized as 4,194,304

words. The device has an 8-bit/16-bit bus and can be

programmed either in the host system or in standard

EPROM programmers.

An access time of 110 ns is available. Each device re-

quires only a single 3.0 volt power supply for both

read and write functions. In addition to a V

CC input, a

high-voltage accelerated program (ACC) feature pro-

vides shorter programming times through increased

current on the WP#/ACC input. This feature is in-

tended to facilitate factory throughput during system

production, but may also be used in the field if desired.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the device using standard

microprocessor write timing. Write cycles also inter-

nally latch addresses and data needed for the pro-

gramming and erase operations.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Device programming and erasure are initiated through

command sequences. Once a program or erase oper-

ation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or

monitor the Ready/Busy# (RY/BY#) output to deter-

mine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces com-

mand sequence overhead by requiring only two write

cycles to program data instead of four.

The Versatile I/O™ (V

IO) control allows the host sys-

tem to set the voltage levels that the device generates

and tolerates on the CE# control input and DQ I/Os to

the same voltage level that is asserted on the V

IO pin.

Refer to the Ordering Information section for valid V

options.

Hardware data protection measures include a low

CC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This can be achieved in-system or via programming

equipment.

The Erase Suspend/Erase Resume feature allows

the host system to pause an erase operation in a given

sector to read or program any other sector and then

complete the erase operation. The Program Sus-

pend/Program Resume feature enables the host sys-

tem to pause a program operation in a given sector to

read any other sector and then complete the program

operation.

The hardware RESET# pin terminates any operation

in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to

read boot-up firmware from the Flash memory device.

T he device reduce s power consumpt ion in the

standby mode when it detects specific voltage levels

on CE# and RESET#, or when addresses have been

stable for a specified period of time.

The Write Protect (WP#) feature protects the first or

last sector by asserting a logic low on the WP#/ACC

pin. The protected sector will still be protected even

during accelerated programming.

The SecSi

™ (Secured Silicon) Sector provides a

128-word area for code or data that can be perma-

nently protected. Once this sector is protected, no fur-

ther changes within the sector can occur.

AMD MirrorBit flash technology combines years of

Flash memory manufacturing experience to produce

the highest levels of quality, reliability and cost effec-

tiveness. The device electrically erases all bits within a

sector simultaneously via hot-hole assisted erase. The

data is programmed using hot electron injection.

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