CC1010-RTR1 datasheet(76/152 Pages) TI

76 / 152 page

CC1010

SWRS047

Page 76 of 152

and DES interrupt enable. When the

encryption

has

been

completed,

CRPCON.CRPEN goes low and the DES

interrupt flag is set. The external RAM will

now contain the encrypted data bit stream

in the same location as the input data

bytes were originally put. To perform the

reverse operation, write CRPCON again

with the CRPCON.ENCDEC bit set.

Key

First RAM Location

Last RAM Location

⋅ CRPKEY

⋅ CRPKEY+6

Table 24. DES key location in RAM

Encryption / decryption is done in-place,

i.e. each byte of data read from external

RAM for encryption / decryption will be

written back to the same location after

encryption / decryption as described

above. The input and output blocks must

start on an address which is a multiple of

eight. CRPDAT then gives the 8 most

significant address bits to the first data

byte.

The encryption / decryption initialization

vector should be written to registers

CRPINI0 to CRPINI7. These registers

must be written prior to encrypting /

decrypting a new block of data, as they

are modified by hardware. They should be

left

unchanged

between

multiple

encryption / decryption operations for DES

blocks larger than 256 bytes. A zero value

initialisation vector can be used, or

additional security can be effected by

using the initialisation vector as an

additional key.

Encryption / decryption is started when

CRPCON.CRPEN

set.

When

the

encryption / decryption is completed,

CRPCON.CRPEN is cleared by hardware

and the interrupt flag CRPCON.CRPIF is

set. If CRPCON.CRPIE is set, the interrupt

flag EXIF.ADIF is also set, which will

generate an interrupt if EIE.ADIE is set.

(See the Interrupts section on page 28 for

details on interrupts.)

The duration of a DES encryption /

decryption operation is shown in Table 25.

Accessing external RAM from the 8051

while encrypting / decrypting may delay

the operation slightly since the access is

multiplexed.

DES keys stored in Flash memory will be

protected by the Flash memory read

protection. For the security of the Flash

protection, please refer to the disclaimer at

the end of this document.

Mode

Duration (clock cycles)

Single DES

2+25

⋅#Data Bytes +21⋅LOADKEYS

Table 25. DES Encryption / Decryption duration

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