ATAM862 datasheet(53/110 Pages) ATMEL

53 / 110 page

4554E–4BMCU–05/06

ATAM862-3

22.11.5

Timer 2 Output Mode 5

Manchester Modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester

code

Figure 22-20. Manchester Modulation

22.11.6

Timer 2 Output Mode 7

In this mode the timer overflow defines the period and the compare register defines the duty

cycle. During one period only the first compare match occurrence is used to toggle the timer out-

put flip-flop, until the overflow all further compare match are ignored. This avoids the situation

that changing the compare register causes the occurrence of several compare match during one

period. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all other

Timer 2 modes are 8-bit.

PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O)

Figure 22-21. PWM Modulation

22.12 Timer 2 Registers

Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and

its output function. All registers are indirectly addressed using extended addressing as

described in section “Addressing Peripherals” on page 32. The alternate functions of the Ports

BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the Timer 2

modes require an input at T2I/BP41 or an output at T2O/BP42.

TOG2

T2O

8-bit SR-Data

Bit 7

Bit 0

Bit 7

Bit 0

Data: 00110101

255

100

255 0

150

255 0 50

255 0

100

T2R

Input clock

Counter 2/2

OVF2

CM2

INT4

T2O

load the next

compare value

T2CO2=150

load

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