ATAM862 datasheet(75/110 Pages) ATMEL

75 / 110 page

4554E–4BMCU–05/06

ATAM862-3

and the SSI will continue clocking in the next telegram. Should, however, the first telegram not

have been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram in

the shift register until a certain point of time when the controller is able to service the receive

buffer. In this way no data is lost or overwritten.

Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch the

present contents of the shift register into the receive buffer. This can be used for clocking in a

data telegram of less than 8 bits in length. Care should be taken to read out the final complete

8-bit data telegram of a multiple word message before deactivating the SSI (SIR = 1) and termi-

nating the reception. After termination, the shift register contents will overwrite the receive

buffer.

Figure 23-17. Example of 8-bit Synchronous Transmit Operation

Figure 23-18. Example of 8-bit Synchronous Receive Operation

76543 21

7 6 5 43 210 7 6 54 321

msb

lsb

tx data 1

tx data 2

tx data 3

msb

lsb msb

lsb

Write STB

(tx data 2)

Write STB

(tx data 3)

Write STB

(tx data 1)

SIR

SRDY

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

ACT

43 21 0

7 6 5 4321 0

msb

lsb

rx data 1

rx data 2

rx data 3

msb

lsb

msb

lsb

Read SRB

(rx data 2)

Read SRB

(rx data 3)

Read SRB

(rx data 1)

SIR

SRDY

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

ACT

76 5

432 1 0

76 5

7 6 5 4

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