ATAM862 datasheet(7/110 Pages) ATMEL

7 / 110 page

4554E–4BMCU–05/06

ATAM862-3

Figure 7-1.

Tolerances of Frequency Modulation

Using C

4 =8.2 pF ±5%, C5 = 10 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray capaci-

tances on each side of the crystal of C

Stray1 =CStray2 = 1 pF ±10%, a parallel capacitance of the

crystal of C

0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, an FSK deviation of ±21.5 kHz

typical with worst case tolerances of ±16.25 kHz to ±28.01 kHz results.

7.3

CLK Output

An output CLK signal is provided for a connected microcontroller, the delivered signal is CMOS

compatible if the load capacitance is lower than 10 pF.

7.3.1

Clock Pulse Take Over

The clock of the crystal oscillator can be used for clocking the microcontroller. The microcontrol-

ler block has the special feature of starting with an integrated RC-oscillator to switch on the PLL

transmitter block with ENABLE = H, and after 1 ms to assume the clock signal of the transmis-

sion IC, so the message can be sent with crystal accuracy.

7.3.2

Output Matching and Power Setting

The output power is set by the load impedance of the antenna. The maximum output power is

achieved with a load impedance of Z

Load,opt =(255+j192) Ω. There must be a low resistive path

to V

S to deliver the DC current.

The delivered current pulse of the power amplifier is 9 mA and the maximum output power is

delivered to a resistive load of 400

Ω if the 1.0 pF output capacitance of the power amplifier is

compensated by the load impedance.

An optimum load impedance of:

Load =400 Ω || j/(2 ×π 1.0 pF) = (255 + j192) Ω thus results for the maximum output power of

8dBm.

The load impedance is defined as the impedance seen from the PLL transmitter block’s ANT1,

ANT2 into the matching network. Do not confuse this large signal load impedance with a small

signal input impedance delivered as input characteristic of RF amplifiers and measured from the

application into the IC instead of from the IC into the application for a power amplifier.

Less output power is achieved by lowering the real parallel part of 400

Ω where the parallel

imaginary part should be kept constant.

Output power measurement can be done with the circuit shown in Figure 7-2 on page 8. Note

that the component values must be changed to compensate the individual board parasitics until

the PLL transmitter block has the right load impedance Z

Load,opt = (255 + j192) Ω. Also the damp-

ing of the cable used to measure the output power must be calibrated.

XTAL

Stray1

Stray2

Crystal equivalent circuit

Switch

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