ATMEGA64-16AI datasheet(28/393 Pages) ATMEL

28 / 393 page

ATmega64(L)

2490L–AVR–10/06

ATmega103 Compatibility

Both External Memory Control Registers, XMCRA and XMCRB, are placed in Extended

I/O space. In ATmega103 compatibility mode, these registers are not available, and the

features selected by these registers are not available. The device is still ATmega103

compatible, as these features did not exist in ATmega103. The limitations in

ATmega103 compatibility mode are:

•

Only two wait-state settings are available (SRW1n = 0b00 and SRW1n = 0b01).

•

The number of bits that are assigned to address high byte are fixed.

•

The external memory section cannot be divided into sectors with different wait-state

settings.

•

Bus Keeper is not available.

•RD, WR, and ALE pins are output only (Port G in ATmega64).

Using the External Memory

Interface

The interface consists of:

•

AD7:0: Multiplexed low-order address bus and data bus.

•

A15:8: High-order address bus (configurable number of bits).

•

ALE: Address latch enable.

•RD: Read strobe.

•WR: Write strobe.

The control bits for the External Memory Interface are located in three registers, the

MCU Control Register – MCUCR, the External Memory Control Register A – XMCRA,

and the External Memory Control Register B – XMCRB.

When the XMEM interface is enabled, the XMEM interface will override the setting in the

Data Direction Registers that corresponds to the ports dedicated to the XMEM interface.

For details about the port override, see the alternate functions in section “I/O Ports” on

page 66. The XMEM interface will auto-detect whether an access is internal or external.

If the access is external, the XMEM interface will output address, data, and the control

signals on the ports according to Figure 13 (this figure shows the wave forms without

wait states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is

low during a data transfer. When the XMEM interface is enabled, also an internal access

will cause activity on address-, data- and ALE ports, but the RD and WR strobes will not

toggle during internal access. When the external memory interface is disabled, the nor-

mal pin and data direction settings are used. Note that when the XMEM interface is

disabled, the address space above the internal SRAM boundary is not mapped into the

internal SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using

an octal latch (typically 74 x 573 or equivalent) which is transparent when G is high.

Address Latch Requirements

Due to the high-speed operation of the XRAM interface, the address latch must be

selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.

When operating at conditions above these frequencies, the typical old style 74HC series

latch becomes inadequate. The external memory interface is designed in compliance to

the 74AHC series latch. However, most latches can be used as long they comply with

the main timing parameters. The main parameters for the address latch are:

•

D to Q propagation delay (t

pd).

•

Data setup time before G low (t

su).

•

Data (address) hold time after G low (

th).

The external memory interface is designed to guaranty minimum address hold time after

G is asserted low of t

h = 5 ns (refer to tLAXX_LD/tLLAXX_ST in Table 137 to Table 144 on

page 339). The D to Q propagation delay (t

pd) must be taken into consideration when

calculating the access time requirement of the external component. The data setup time

ATMEGA64-16AI датащи(PDF) 28 Page - ATMEL Corporation

ATMEGA64-16AI датащи(HTML) 28 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL